This patchset mainly provides necessary EDAC bits to decode errors
occuring on Scalable MCA enabled processors and also updates AMD MCE
driver to program the correct MCx_MISC register address for upcoming
processors.
Patches 1, 2 and 3 are meant for the upcoming processors.
Patches 4 and 5 are either fixing or adding comments to help in
understanding the code and do not introduce any functional changes.
Patch 1: Move MSR definition to mce.h
Patch 2: Updates to EDAC driver to decode the new error signatures
Patch 3: Fix logic to obtain correct block address
Patch 4: Fix deferred error comment
Patch 5: Add comments to amd_nb.h to describe threshold_block structure
Tested V2 patches for regressions on Fam15h, Fam10h systems
and found none.
Note 1: Introduced new patch for moving MCx_CONFIG MSR to mce.h
Note 2: The enums ans amd_hwid_mappings[] array are placed in arch/x86
as there are follow-up patches which need the struct there
Changes from V1: (per Boris suggestions)
- Simplify error decoding routines
- Move headers to mce.h
- Rename enumerations and struct members (to be more descriptive)
- Drop gerund usage
- Remove comments that are spelling out the code
Aravind Gopalakrishnan (5):
x86/mce: Move MCx_CONFIG MSR definition
EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
x86/mce/AMD: Fix logic to obtain block address
x86/mce: Clarify comments regarding deferred error
x86/mce/AMD: Add comments for easier understanding
arch/x86/include/asm/amd_nb.h | 18 +-
arch/x86/include/asm/mce.h | 63 ++++++-
arch/x86/include/asm/msr-index.h | 4 -
arch/x86/kernel/cpu/mcheck/mce_amd.c | 108 +++++++----
drivers/edac/mce_amd.c | 342 ++++++++++++++++++++++++++++++++++-
5 files changed, 486 insertions(+), 49 deletions(-)
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2.7.0
