Number of interrupts per each chip is determined when IRQ controller
allocates IRQ chip by calling irq_alloc_domain_generic_chips().
This number is fixed by atmel-aic-common part. The value is 32.
So each AIC driver can use this value directly in IRQ chip operation.
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Alexandre Belloni <alexandre.bell...@free-electrons.com>
Cc: Boris BREZILLON <boris.brezil...@free-electrons.com>
Cc: Ludovic Desroches <ludovic.desroc...@atmel.com>
Cc: Nicolas Ferre <nicolas.fe...@atmel.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Milo Kim <milo....@ti.com>
---
drivers/irqchip/irq-atmel-aic.c | 2 +-
drivers/irqchip/irq-atmel-aic5.c | 9 +++------
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c
index c499949..f2c0fd9 100644
--- a/drivers/irqchip/irq-atmel-aic.c
+++ b/drivers/irqchip/irq-atmel-aic.c
@@ -188,7 +188,7 @@ static int aic_irq_domain_xlate(struct irq_domain *d,
if (ret)
return ret;
- idx = intspec[0] / dgc->irqs_per_chip;
+ idx = intspec[0] / AIC_IRQS_PER_CHIP;
if (idx >= dgc->num_chips)
return -EINVAL;
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index f5848c8..50d540b 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -153,14 +153,13 @@ static int aic5_set_type(struct irq_data *d, unsigned
type)
static void aic5_suspend(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
- struct irq_domain_chip_generic *dgc = domain->gc;
struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int i;
u32 mask;
irq_gc_lock(bgc);
- for (i = 0; i < dgc->irqs_per_chip; i++) {
+ for (i = 0; i < AIC_IRQS_PER_CHIP; i++) {
mask = 1 << i;
if ((mask & gc->mask_cache) == (mask & gc->wake_active))
continue;
@@ -177,14 +176,13 @@ static void aic5_suspend(struct irq_data *d)
static void aic5_resume(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
- struct irq_domain_chip_generic *dgc = domain->gc;
struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int i;
u32 mask;
irq_gc_lock(bgc);
- for (i = 0; i < dgc->irqs_per_chip; i++) {
+ for (i = 0; i < AIC_IRQS_PER_CHIP; i++) {
mask = 1 << i;
if ((mask & gc->mask_cache) == (mask & gc->wake_active))
continue;
@@ -201,13 +199,12 @@ static void aic5_resume(struct irq_data *d)
static void aic5_pm_shutdown(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
- struct irq_domain_chip_generic *dgc = domain->gc;
struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
int i;
irq_gc_lock(bgc);
- for (i = 0; i < dgc->irqs_per_chip; i++) {
+ for (i = 0; i < AIC_IRQS_PER_CHIP; i++) {
irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
--
2.6.4
--
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