On Tuesday 29 December 2015 21:33:52 Rongrong Zou wrote:
> Signed-off-by: Rongrong Zou <zourongr...@gmail.com>
> ---
> .../devicetree/bindings/arm64/low-pin-count.txt | 20
> ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt
>
> diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt
> b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
> new file mode 100644
> index 0000000..215f2c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
> @@ -0,0 +1,20 @@
> +Low Pin Count bus driver
> +
> +Usually LPC controller is part of PCI host bridge, so the legacy ISA
> +port locate on LPC bus can be accessed directly. But some SoC have
> +independent LPC controller, and we can access the legacy port by specifying
> +LPC address cycle. Thus, LPC driver is introduced.
> +
> +Required properties:
> +- compatible: "low-pin-count"
> +- reg: specifies low pin count address range
> +
> +
> +Example:
> +
> + lpc_0: lpc@a01b0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "low-pin-count";
> + reg = <0x0 0xa01b0000 0x0 0x10000>;
> + };
One more thought: please try to stick as closely as possible to the existing
ISA binding that is documented at
http://www.firmware.org/1275/bindings/isa/isa0_4d.ps
In particular, this should cover the possibility of describing both memory
and I/O spaces in child devices.
Arnd
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