On Sun, Dec 20, 2015 at 7:11 PM, Måns Rullgård <m...@mansr.com> wrote: > Julian Margetson <runa...@candw.ms> writes: > >> On 12/19/2015 4:41 PM, Måns Rullgård wrote: >>> Andy Shevchenko <andy.shevche...@gmail.com> writes: >>> >>>> On Sat, Dec 19, 2015 at 10:16 PM, Julian Margetson <runa...@candw.ms> >>>> wrote: >>>>> On 12/19/2015 3:07 PM, Måns Rullgård wrote: >>>>>> Julian Margetson <runa...@candw.ms> writes:
>> [ 18.606292] dma dma0chan0: dwc_tx_submit: queued 2 >> [ 18.611091] dma dma0chan0: dwc_dostart_first_queued: started 2 >> [ 48.748614] ata3: lost interrupt (Status 0x40) > > Now we're getting somewhere. The dma transfer is set up and initiated, > but then nothing happens. Comparing the old sata_dwc driver, from > before the switch to dmaengine, with the dw_dma driver, I noticed an > obvious problem: the descriptors are filled in using the wrong byte > order. So, it means we have IO in little endian, but DMA reads data from memory in big endian? > This patch might fix that. In case it works I have to test it on AVR32. -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
