On 25/11/2015 13:12, Måns Rullgård wrote:
> Mason writes:
>
>>> + status_lo = intc_readl(chip, chip->ctl + IRQ_STATUS);
>>> + status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS);
>>
>> In my local branch, I wrote:
>>
>> #define IRQ_CTL_LO 0
>>
>> status_lo = intc_readl(chip, chip->ctl + IRQ_CTL_LO + IRQ_STATUS);
>> status_hi = intc_readl(chip, chip->ctl + IRQ_CTL_HI + IRQ_STATUS);
>>
>> (I'm a sucker for symmetry)
>
> Nothing wrong with a little symmetry, though in this case I think the
> extra macro only confuses matters.
It's your call :-)
In my mind, the fact that the status_lo register sits at offset 0 is
just an accident. It's just that something has to sit at offset 0.
(Maybe I should tell the HW guys to put nothing at offset 0, and start
the actual register block at offset 4. /That/ would be unexpected.)
Another way to look at it is:
There are two 4-register blocks (LO and HI) each containing registers
{status,rawstat,enableset,enableclr}.
Block LO starts at offset 0x0
Block HI starts at offset 0x18
and then there are the intra offsets for the 4 registers in the block.
There! I got the bike-shedding out of my system ;-)
Regards.
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