On Sat, 2006-12-09 at 01:25 +0000, Ralf Baechle wrote:
> On Fri, Dec 08, 2006 at 07:46:18PM -0500, Ben Collins wrote:
>
> > On Wed, 2006-12-06 at 13:41 +0000, Ralf Baechle wrote:
> > > Since commit 368c73d4f689dae0807d0a2aa74c61fd2b9b075f the kernel will try
> > > to update the non-writeable BAR registers 0..3 of PIIX4 IDE adapters if
> > > pci_assign_unassigned_resources() is used to do full resource assignment
> > > of the bus. This fails because in the PIIX4 these BAR registers have
> > > implicitly assumed values and read back as zero; it used to work because
> > > the kernel used to just write zero to that register the read back value
> > > did match what was written.
> > >
> > > The fix is a new resource flag IORESOURCE_PCI_FIXED used to mark a
> > > resource as non-movable. This will also be useful to keep other import
> > > system resources from being moved around - for example system consoles
> > > on PCI busses.
> >
> > I have a problem where an ich6 (SATA+PATA) is getting its port0 reserved
> > by the pci quirk for libata so that it gets picked up by ata_piix. In
> > current git, ata_piix complains:
> >
> > [ 124.507570] PCI: Unable to reserve I/O region #1:[EMAIL PROTECTED] for
> > device 0000:00:1f.2
> >
> > I bisected to the same commit, 368c73d4f689dae0807d0a2aa74c61fd2b9b075f,
> > however, your patch doesn't fix my problem.
>
> Looks like a double reservation. My patch doesn't deal with reservations
> at all. I thought about resource reservations but decieded that should
> be dealt with elsewhere.
Checking the patch, my problem is that the old way, all BAR's were being
set at start = end = flags = 0. The patch makes it set all the BAR's to
the normal values. This is what it looks like in lspci, pre this patch:
Region 0: I/O ports at <unassigned>
Region 1: I/O ports at <unassigned>
Region 2: I/O ports at <unassigned>
Region 3: I/O ports at <unassigned>
So my device is not running in compatibility mode, and should not have
the BAR's set, as Alan's patch does.
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