On Tue, Aug 26, 2025 at 11:47:45AM -0400, Frank Li wrote:
> On Mon, Aug 18, 2025 at 01:51:13PM +0200, Jorge Marques wrote:
> > Add bindings doc for ADI I3C Controller IP core, a FPGA synthesizable IP
> > core that implements the MIPI I3C Basic controller specification.
> > The IP Core is versioned following Semantic Versioning 2.0.0 and
> > ADI's open-source HDL guidelines for devicetree bindings and drivers.
> >
> > Signed-off-by: Jorge Marques <[email protected]>
> > ---
> > .../devicetree/bindings/i3c/adi,i3c-master.yaml | 72
> > ++++++++++++++++++++++
> > MAINTAINERS | 5 ++
> > 2 files changed, 77 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml
> > b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml
> > new file mode 100644
> > index
> > 0000000000000000000000000000000000000000..fda240f9ee0c73bcbea97f775d6e081fe0c089d9
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> ...
> > +
> > + clocks:
> > + minItems: 1
> > + items:
> > + - description: The AXI interconnect clock, drives the register map.
> > + - description: |
>
> Needn't | here.
>
> Frank
Ack
Best regards,
Jorge
> > + The secondary clock, drives the internal logic asynchronously to
> > the
> > + register map. The presence of this entry states that the IP Core
> > was
> > + synthesized with a second clock input, and the absence of this
> > entry
> > + indicates a topology where a single clock input drives all the
> > + internal logic.
> > +
> > + clock-names:
> > + minItems: 1
> > + items:
> > + - const: axi
> > + - const: i3c
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > +
> > +allOf:
> > + - $ref: i3c.yaml#
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > +
> > + i3c@44a00000 {
> > + compatible = "adi,i3c-master-v1";
> > + reg = <0x44a00000 0x1000>;
> > + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clkc 15>, <&clkc 15>;
> > + clock-names = "axi", "i3c";
> > + #address-cells = <3>;
> > + #size-cells = <0>;
> > +
> > + /* I3C and I2C devices */
> > + };
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index
> > 35ed8498ab1e9b92b4bce5db9bb64004d80e4b1a..faa50535b514037ddf97309874ec64aac2013cb6
> > 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -11452,6 +11452,11 @@ S: Maintained
> > F: Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
> > F: drivers/i3c/master/ast2600-i3c-master.c
> >
> > +I3C DRIVER FOR ANALOG DEVICES I3C CONTROLLER IP
> > +M: Jorge Marques <[email protected]>
> > +S: Maintained
> > +F: Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml
> > +
> > I3C DRIVER FOR CADENCE I3C MASTER IP
> > M: Przemysław Gaj <[email protected]>
> > S: Maintained
> >
> > --
> > 2.49.0
> >
