On Mon, Apr 21, 2025 at 5:20 PM Rob Herring <[email protected]> wrote: > > On Wed, Apr 16, 2025 at 06:21:37PM +0200, Ivan Vecera wrote: > > Add a common DT schema for DPLL device and associated pin. > > The DPLL (device phase-locked loop) is a device used for precise clock > > synchronization in networking and telecom hardware. > > In the subject, drop 'device tree binding for'. You already said that > with 'dt-bindings'. > > > > > The device itself is equipped with one or more DPLLs (channels) and > > one or more physical input and output pins. > > > > Each DPLL channel is used either to provide pulse-per-clock signal or > > to drive ethernet equipment clock. > > > > The input and output pins have a label (specifies board label), > > type (specifies its usage depending on wiring), list of supported > > or allowed frequencies (depending on how the pin is connected and > > where) and can support embedded sync capability. > > Convince me this is something generic... Some example parts or > datasheets would help. For example, wouldn't these devices have 1 or > more power supplies or a reset line?
Never mind, I read the next patch... > > > > > Signed-off-by: Ivan Vecera <[email protected]> > > --- > > v1->v3: > > * rewritten description for both device and pin > > * dropped num-dplls property > > * supported-frequencies property renamed to supported-frequencies-hz > > --- > > .../devicetree/bindings/dpll/dpll-device.yaml | 76 +++++++++++++++++++ > > .../devicetree/bindings/dpll/dpll-pin.yaml | 44 +++++++++++ > > MAINTAINERS | 2 + > > 3 files changed, 122 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/dpll/dpll-device.yaml > > create mode 100644 Documentation/devicetree/bindings/dpll/dpll-pin.yaml > > > > diff --git a/Documentation/devicetree/bindings/dpll/dpll-device.yaml > > b/Documentation/devicetree/bindings/dpll/dpll-device.yaml > > new file mode 100644 > > index 0000000000000..11a02b74e28b7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dpll/dpll-device.yaml > > @@ -0,0 +1,76 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/dpll/dpll-device.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Digital Phase-Locked Loop (DPLL) Device > > + > > +maintainers: > > + - Ivan Vecera <[email protected]> > > + > > +description: > > + Digital Phase-Locked Loop (DPLL) device is used for precise clock > > + synchronization in networking and telecom hardware. The device can > > + have one or more channels (DPLLs) and one or more physical input and > > + output pins. Each DPLL channel can either produce pulse-per-clock signal > > + or drive ethernet equipment clock. The type of each channel can be > > + indicated by dpll-types property. > > + > > +properties: > > + $nodename: > > + pattern: "^dpll(@.*)?$" > > There's no 'reg' property, so you can't ever have a unit-address. I > suppose you can have more than 1, so you need a '-[0-9]+' suffix. And forget this too. Rob
