On Mon, Mar 31, 2025 at 05:43:15PM +0800, Yicong Yang wrote:
> From: Yicong Yang <yangyic...@hisilicon.com>
>
> Instructions introduced by FEAT_{LS64, LS64_V} is controlled by
> HCRX_EL2.{EnALS, EnASR}. Configure all of these to allow usage
> at EL0/1.
>
> This doesn't mean these instructions are always available in
> EL0/1 if provided. The hypervisor still have the control at
> runtime.
>
> Signed-off-by: Yicong Yang <yangyic...@hisilicon.com>
> ---
> arch/arm64/include/asm/el2_setup.h | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/el2_setup.h
> b/arch/arm64/include/asm/el2_setup.h
> index ebceaae3c749..0259941602c4 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -57,9 +57,19 @@
> /* Enable GCS if supported */
> mrs_s x1, SYS_ID_AA64PFR1_EL1
> ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4
> - cbz x1, .Lset_hcrx_\@
> + cbz x1, .Lskip_gcs_hcrx_\@
> orr x0, x0, #HCRX_EL2_GCSEn
>
> +.Lskip_gcs_hcrx_\@:
> + /* Enable LS64, LS64_V if supported */
> + mrs_s x1, SYS_ID_AA64ISAR1_EL1
> + ubfx x1, x1, #ID_AA64ISAR1_EL1_LS64_SHIFT, #4
> + cbz x1, .Lset_hcrx_\@
> + orr x0, x0, #HCRX_EL2_EnALS
> + cmp x1, #ID_AA64ISAR1_EL1_LS64_LS64_V
> + b.lt .Lset_hcrx_\@
> + orr x0, x0, #HCRX_EL2_EnASR
How do these HCRX settings survive a world-switch to and from a KVM
guest? AFAICT, the trap deactivation path there restores HCRX_HOST_FLAGS
when returning to the host. That would mean that the GCS code is broken
too, unless I'm missing something :/
Will
