On Wed, Aug 21, 2019 at 05:47:29PM +0100, Catalin Marinas wrote: > From: Vincenzo Frascino <vincenzo.frasc...@arm.com> > > On AArch64 the TCR_EL1.TBI0 bit is set by default, allowing userspace > (EL0) to perform memory accesses through 64-bit pointers with a non-zero > top byte. Introduce the document describing the relaxation of the > syscall ABI that allows userspace to pass certain tagged pointers to > kernel syscalls. > > Cc: Will Deacon <will.dea...@arm.com> > Cc: Andrey Konovalov <andreyk...@google.com> > Cc: Szabolcs Nagy <szabolcs.n...@arm.com> > Cc: Kevin Brodsky <kevin.brod...@arm.com> > Signed-off-by: Vincenzo Frascino <vincenzo.frasc...@arm.com> > Co-developed-by: Catalin Marinas <catalin.mari...@arm.com> > Signed-off-by: Catalin Marinas <catalin.mari...@arm.com> > --- > Documentation/arm64/tagged-address-abi.rst | 156 +++++++++++++++++++++ > 1 file changed, 156 insertions(+) > create mode 100644 Documentation/arm64/tagged-address-abi.rst
Thanks, I'll pick this on up. Will
