On Fri, Jun 07, 2019 at 04:14:07PM +0100, James Morse wrote: > "L2 cache does not support code and data prioritization". This isn't > true, elsewhere the document says it can be enabled with the cdpl2 > mount option. > > While we're here, these sample strings have lower-case code/data, > which isn't how the kernel exports them. > > Signed-off-by: James Morse <james.mo...@arm.com> > --- > Documentation/x86/resctrl_ui.rst | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/Documentation/x86/resctrl_ui.rst > b/Documentation/x86/resctrl_ui.rst > index 066f94e53418..638cd987937d 100644 > --- a/Documentation/x86/resctrl_ui.rst > +++ b/Documentation/x86/resctrl_ui.rst > @@ -418,16 +418,22 @@ L3 schemata file details (CDP enabled via mount option > to resctrl) > When CDP is enabled L3 control is split into two separate resources > so you can specify independent masks for code and data like this:: > > - L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > - L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > + L3DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > + L3CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > > L2 schemata file details > ------------------------ > -L2 cache does not support code and data prioritization, so the > -schemata format is always:: > +CDP is supported at L2 using the 'cdpl2' mount option. The schemata > +format is either:: > > L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > > +or > + > + L2DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > + L2CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;... > + > + > Memory bandwidth Allocation (default mode) > ------------------------------------------ > > -- > 2.20.1 >
Acked-by: Fenghua Yu <fenghua...@intel.com> Thanks. -Fenghua
