On Mon, Nov 26, 2018 at 04:52:14PM +0000, Will Deacon wrote:
> David Laight explains:
>
> | A long time ago there was a document from Intel that said that
> | inb/outb weren't necessarily synchronised wrt memory accesses.
> | (Might be P-pro era). However no processors actually behaved that
> | way and more recent docs say that inb/outb are fully ordered.
>
> This also reflects the situation on other architectures, the the port
> accessor macros tend to be implemented in terms of readX/writeX.
>
> Update Documentation/memory-barriers.txt to reflect reality.
>
> Cc: Benjamin Herrenschmidt <b...@kernel.crashing.org>
> Cc: Arnd Bergmann <a...@arndb.de>
> Cc: David Laight <david.lai...@aculab.com>
> Cc: Alan Stern <st...@rowland.harvard.edu>
> Cc: Peter Zijlstra <pet...@infradead.org>
> Cc: "Paul E. McKenney" <paul...@linux.vnet.ibm.com>
> Signed-off-by: Will Deacon <will.dea...@arm.com>
Queued, with the addition of Cc: of LKML, linux-arch, and linux-docs,
thank you!
(Otherwise, these lists can get lost when I send out the LKMM series.)
Thanx, Paul
> ---
>
> Just remembered I had this patch kicking around in my tree...
>
> Documentation/memory-barriers.txt | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt
> b/Documentation/memory-barriers.txt
> index c1d913944ad8..0c34c5dac138 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -2619,10 +2619,8 @@ functions:
> intermediary bridges (such as the PCI host bridge) may not fully honour
> that.
>
> - They are guaranteed to be fully ordered with respect to each other.
> -
> - They are not guaranteed to be fully ordered with respect to other types
> of
> - memory and I/O operation.
> + They are guaranteed to be fully ordered with respect to each other and
> + also with respect to other types of memory and I/O operation.
>
> (*) readX(), writeX():
>
> --
> 2.1.4
>
