Commit-ID: aa50453a448ad645ea05788505680aa403934aa8 Gitweb: https://git.kernel.org/tip/aa50453a448ad645ea05788505680aa403934aa8 Author: Babu Moger <babu.mo...@amd.com> AuthorDate: Wed, 21 Nov 2018 20:28:31 +0000 Committer: Borislav Petkov <b...@suse.de> CommitDate: Thu, 22 Nov 2018 20:16:19 +0100
x86/resctrl: Move all the macros to resctrl/internal.h Move all the macros to resctrl/internal.h and rename the registers with MSR_ prefix for consistency. [bp: align MSR definitions vertically ] Signed-off-by: Babu Moger <babu.mo...@amd.com> Signed-off-by: Borislav Petkov <b...@suse.de> Cc: Andrew Morton <a...@linux-foundation.org> Cc: Andy Lutomirski <l...@kernel.org> Cc: Arnd Bergmann <a...@arndb.de> Cc: Brijesh Singh <brijesh.si...@amd.com> Cc: "Chang S. Bae" <chang.seok....@intel.com> Cc: David Miller <da...@davemloft.net> Cc: David Woodhouse <dw...@infradead.org> Cc: Dmitry Safonov <d...@arista.com> Cc: Fenghua Yu <fenghua...@intel.com> Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org> Cc: "H. Peter Anvin" <h...@zytor.com> Cc: Ingo Molnar <mi...@redhat.com> Cc: Jann Horn <ja...@google.com> Cc: Joerg Roedel <jroe...@suse.de> Cc: Jonathan Corbet <cor...@lwn.net> Cc: Josh Poimboeuf <jpoim...@redhat.com> Cc: Kate Stewart <kstew...@linuxfoundation.org> Cc: "Kirill A. Shutemov" <kirill.shute...@linux.intel.com> Cc: <linux-doc@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab+sams...@kernel.org> Cc: Paolo Bonzini <pbonz...@redhat.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Philippe Ombredanne <pombreda...@nexb.com> Cc: Pu Wen <pu...@hygon.cn> Cc: <qianyue...@alibaba-inc.com> Cc: "Rafael J. Wysocki" <raf...@kernel.org> Cc: Reinette Chatre <reinette.cha...@intel.com> Cc: Rian Hunter <r...@alum.mit.edu> Cc: Sherry Hurwitz <sherry.hurw...@amd.com> Cc: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: Thomas Lendacky <thomas.lenda...@amd.com> Cc: Tony Luck <tony.l...@intel.com> Cc: Vitaly Kuznetsov <vkuzn...@redhat.com> Cc: <xiaochen.s...@intel.com> Link: https://lkml.kernel.org/r/20181121202811.4492-5-babu.mo...@amd.com --- arch/x86/kernel/cpu/resctrl/core.c | 22 ++++++++++------------ arch/x86/kernel/cpu/resctrl/internal.h | 19 ++++++++++++------- arch/x86/kernel/cpu/resctrl/monitor.c | 3 --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 40380731c588..cf6491eeadc6 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -33,9 +33,6 @@ #include <asm/resctrl_sched.h> #include "internal.h" -#define MBA_IS_LINEAR 0x4 -#define MBA_MAX_MBPS U32_MAX - /* Mutex to protect rdtgroup access. */ DEFINE_MUTEX(rdtgroup_mutex); @@ -72,7 +69,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3, .name = "L3", .domains = domain_init(RDT_RESOURCE_L3), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -89,7 +86,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3DATA, .name = "L3DATA", .domains = domain_init(RDT_RESOURCE_L3DATA), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -106,7 +103,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3CODE, .name = "L3CODE", .domains = domain_init(RDT_RESOURCE_L3CODE), - .msr_base = IA32_L3_CBM_BASE, + .msr_base = MSR_IA32_L3_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 3, .cache = { @@ -123,7 +120,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2, .name = "L2", .domains = domain_init(RDT_RESOURCE_L2), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -140,7 +137,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2DATA, .name = "L2DATA", .domains = domain_init(RDT_RESOURCE_L2DATA), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -157,7 +154,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2CODE, .name = "L2CODE", .domains = domain_init(RDT_RESOURCE_L2CODE), - .msr_base = IA32_L2_CBM_BASE, + .msr_base = MSR_IA32_L2_CBM_BASE, .msr_update = cat_wrmsr, .cache_level = 2, .cache = { @@ -174,7 +171,7 @@ struct rdt_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_MBA, .name = "MB", .domains = domain_init(RDT_RESOURCE_MBA), - .msr_base = IA32_MBA_THRTL_BASE, + .msr_base = MSR_IA32_MBA_THRTL_BASE, .msr_update = mba_wrmsr, .cache_level = 3, .parse_ctrlval = parse_bw, @@ -211,9 +208,10 @@ static inline void cache_alloc_hsw_probe(void) struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3]; u32 l, h, max_cbm = BIT_MASK(20) - 1; - if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0)) + if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0)) return; - rdmsr(IA32_L3_CBM_BASE, l, h); + + rdmsr(MSR_IA32_L3_CBM_BASE, l, h); /* If all the bits were set in MSR, return success */ if (l != max_cbm) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index eeaee05522b5..fb26d347ae6c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -6,15 +6,18 @@ #include <linux/kernfs.h> #include <linux/jump_label.h> -#define IA32_L3_QOS_CFG 0xc81 -#define IA32_L2_QOS_CFG 0xc82 -#define IA32_L3_CBM_BASE 0xc90 -#define IA32_L2_CBM_BASE 0xd10 -#define IA32_MBA_THRTL_BASE 0xd50 +#define MSR_IA32_L3_QOS_CFG 0xc81 +#define MSR_IA32_L2_QOS_CFG 0xc82 +#define MSR_IA32_L3_CBM_BASE 0xc90 +#define MSR_IA32_L2_CBM_BASE 0xd10 +#define MSR_IA32_MBA_THRTL_BASE 0xd50 -#define L3_QOS_CDP_ENABLE 0x01ULL +#define MSR_IA32_QM_CTR 0x0c8e +#define MSR_IA32_QM_EVTSEL 0x0c8d -#define L2_QOS_CDP_ENABLE 0x01ULL +#define L3_QOS_CDP_ENABLE 0x01ULL + +#define L2_QOS_CDP_ENABLE 0x01ULL /* * Event IDs are used to program IA32_QM_EVTSEL before reading event @@ -29,6 +32,8 @@ #define MBM_CNTR_WIDTH 24 #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u +#define MBA_IS_LINEAR 0x4 +#define MBA_MAX_MBPS U32_MAX #define RMID_VAL_ERROR BIT_ULL(63) #define RMID_VAL_UNAVAIL BIT_ULL(62) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index ebf408db8191..f33f11f69078 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -28,9 +28,6 @@ #include <asm/cpu_device_id.h> #include "internal.h" -#define MSR_IA32_QM_CTR 0x0c8e -#define MSR_IA32_QM_EVTSEL 0x0c8d - struct rmid_entry { u32 rmid; int busy; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 2bf1f3227afa..cf159095b612 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1722,14 +1722,14 @@ static void l3_qos_cfg_update(void *arg) { bool *enable = arg; - wrmsrl(IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); + wrmsrl(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); } static void l2_qos_cfg_update(void *arg) { bool *enable = arg; - wrmsrl(IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); + wrmsrl(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); } static inline bool is_mba_linear(void)
