Indirect branch tracking provides an optional legacy code bitmap
that indicates locations of non-IBT compatible code. When set,
each bit in the bitmap represents a page in the linear address is
legacy code.
We allocate the bitmap only when the application requests it.
Most applications do not need the bitmap.
Signed-off-by: Yu-cheng Yu <yu-cheng...@intel.com>
---
arch/x86/kernel/cet.c | 47 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
index 40c4c08e5e31..77ae4eaa9dea 100644
--- a/arch/x86/kernel/cet.c
+++ b/arch/x86/kernel/cet.c
@@ -21,6 +21,7 @@
#include <asm/compat.h>
#include <asm/cet.h>
#include <asm/special_insns.h>
+#include <asm/elf.h>
static int set_shstk_ptr(unsigned long addr)
{
@@ -327,3 +328,49 @@ void cet_disable_ibt(void)
wrmsrl(MSR_IA32_U_CET, r);
current->thread.cet.ibt_enabled = 0;
}
+
+int cet_setup_ibt_bitmap(void)
+{
+ u64 r;
+ unsigned long bitmap;
+ unsigned long size;
+
+ if (!cpu_feature_enabled(X86_FEATURE_IBT))
+ return -EOPNOTSUPP;
+
+ if (!current->thread.cet.ibt_bitmap_addr) {
+ /*
+ * Calculate size and put in thread header.
+ * may_expand_vm() needs this information.
+ */
+ size = in_compat_syscall() ? task_size_32bit() :
task_size_64bit(1);
+ size = size / PAGE_SIZE / BITS_PER_BYTE;
+ current->thread.cet.ibt_bitmap_size = size;
+ bitmap = do_mmap_locked(0, size, PROT_READ | PROT_WRITE,
+ MAP_ANONYMOUS | MAP_PRIVATE,
+ VM_DONTDUMP);
+
+ if ((bitmap >= TASK_SIZE) || (bitmap < size)) {
+ current->thread.cet.ibt_bitmap_size = 0;
+ return -ENOMEM;
+ }
+
+ current->thread.cet.ibt_bitmap_addr = bitmap;
+
+ /*
+ * Lower bits of MSR_IA32_CET_LEG_IW_EN are for IBT
+ * settings. Clear lower bits even bitmap is already
+ * page-aligned.
+ */
+ bitmap &= PAGE_MASK;
+
+ /*
+ * Turn on IBT legacy bitmap.
+ */
+ rdmsrl(MSR_IA32_U_CET, r);
+ r |= (MSR_IA32_CET_LEG_IW_EN | bitmap);
+ wrmsrl(MSR_IA32_U_CET, r);
+ }
+
+ return 0;
+}
--
2.17.1
