On Wed, 2018-10-03 at 21:57 +0200, Eugene Syromiatnikov wrote:
> On Fri, Sep 21, 2018 at 08:05:47AM -0700, Yu-cheng Yu wrote:
> > Indirect branch tracking provides an optional legacy code bitmap
> > that indicates locations of non-IBT compatible code. When set,
> > each bit in the bitmap represents a page in the linear address is
> > legacy code.
> >
> > We allocate the bitmap only when the application requests it.
> > Most applications do not need the bitmap.
> >
> > Signed-off-by: Yu-cheng Yu <yu-cheng...@intel.com>
> > ---
> > arch/x86/kernel/cet.c | 45 +++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 45 insertions(+)
> >
> > diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
> > index 6adfe795d692..a65d9745af08 100644
> > --- a/arch/x86/kernel/cet.c
> > +++ b/arch/x86/kernel/cet.c
> > @@ -314,3 +314,48 @@ void cet_disable_ibt(void)
> > wrmsrl(MSR_IA32_U_CET, r);
> > current->thread.cet.ibt_enabled = 0;
> > }
> > +
> > +int cet_setup_ibt_bitmap(void)
> > +{
> > + u64 r;
> > + unsigned long bitmap;
> > + unsigned long size;
> > +
> > + if (!cpu_feature_enabled(X86_FEATURE_IBT))
> > + return -EOPNOTSUPP;
> > +
> > + if (!current->thread.cet.ibt_bitmap_addr) {
> > + /*
> > + * Calculate size and put in thread header.
> > + * may_expand_vm() needs this information.
> > + */
> > + size = TASK_SIZE / PAGE_SIZE / BITS_PER_BYTE;
>
> TASK_SIZE_MAX is likely needed here, as an application can easily switch
> between long an 32-bit protected mode. And then the case of a CPU that
> doesn't support 5LPT.
If we had calculated bitmap size from TASK_SIZE_MAX, all 32-bit apps would have
failed the allocation for bitmap size > TASK_SIZE. Please see values below,
which is printed from the current code.
Yu-cheng
x64:
TASK_SIZE_MAX = 0000 7fff ffff f000
TASK_SIZE = 0000 7fff ffff f000
bitmap size = 0000 0000 ffff ffff
x32:
TASK_SIZE_MAX = 0000 7fff ffff f000
TASK_SIZE = 0000 0000 ffff e000
bitmap size = 0000 0000 0001 ffff
