+ Toshi.
On Wed, Nov 09, 2016 at 06:34:48PM -0600, Tom Lendacky wrote:
> For processors that support PAT, set the write-protect cache mode
> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).
>
> Acked-by: Borislav Petkov <b...@suse.de>
> Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
> ---
> arch/x86/mm/pat.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
> index 170cc4f..87e8952 100644
> --- a/arch/x86/mm/pat.c
> +++ b/arch/x86/mm/pat.c
> @@ -355,7 +355,7 @@ void pat_init(void)
> * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS
> * 011 3 UC : _PAGE_CACHE_MODE_UC
> * 100 4 WB : Reserved
> - * 101 5 WC : Reserved
> + * 101 5 WP : _PAGE_CACHE_MODE_WP
> * 110 6 UC-: Reserved
> * 111 7 WT : _PAGE_CACHE_MODE_WT
> *
> @@ -363,7 +363,7 @@ void pat_init(void)
> * corresponding types in the presence of PAT errata.
> */
> pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) |
> - PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT);
> + PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT);
> }
>
> if (!boot_cpu_done) {
>
>
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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