Hello, I have two questions:
1- I was wondering what should be the expected semantics of "flush_cache_all" on a Big.LITTLE architecture. I can see that the implementation of this function under linux kernel is doing the following: a- Read the value of LoC ( level of coherency ) b- Flush each level of cache to that LoC value using DCCISW co-processor register. My expectation would be that if this is executed on one of the processors of the Big cluster it should flush all L1 and L2 caches on this cluster and then signal the CCI interconnect of the cache cleaning operation and then the CCI interconnect would propagate this signal downstream to the LITTLE cluster. This will mean that at the end all cache will be flushed. Is that the proper semantics of this operation ? or it's only going to affect this CPU and no other CPUs in the cluster ( and consequently no other CPUs on the other cluster ). And if that's the case, does this mean that I've to do the cache flushing per_cpu ? 2- and Is there a difference in semantics between flushing each cache till I reach the Level of coherency ( using DCCISW register ) and flushing the first cache only to the point of coherency ( using DCCIMVAC register ) ? Thanks. -- Karim Allah Ahmed. _______________________________________________ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
