Hi Nico, Liviu, Catalin, Do you expect there to also be cases where the PSCI interface may not be aware of all of the platform states?
Eg. if you have an SOC, not all of the cstates and latencies are directly related to the ARM core.. Maybe you can have additional states and latencies accounting for the cost of enabling external power supplies, restoring state for non-retained peripherals/hw, etc. Currently, this type of thing can be specified in cpuidle with aditional cstates and handled in vendor specific sw, with the additional cstates being selected when the TR/latency requirements are least restrictive. How would these states be handled considering also host os costs? Thanks, Sebastian _______________________________________________ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
