Hi Igor,
On 25 January 2012 12:26, Igor Grinberg <grinb...@compulab.co.il> wrote:
> Hi Chander,
>
> On 01/25/12 07:19, Chander Kashyap wrote:
>> SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
>>
>> Signed-off-by: Chander Kashyap <chander.kash...@linaro.org>
>> ---
>
> [...]
>
>> diff --git a/board/samsung/smdk5250/dmc_init.c
>> b/board/samsung/smdk5250/dmc_init.c
>> new file mode 100644
>> index 0000000..6f92d8a
>> --- /dev/null
>> +++ b/board/samsung/smdk5250/dmc_init.c
>> @@ -0,0 +1,508 @@
>> +/*
>> + * Memory setup for SMDK5250 board based on EXYNOS5
>> + *
>> + * Copyright (C) 2011 Samsung Electronics
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <config.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/dmc.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cpu.h>
>> +#include "setup.h"
>> +
>> +/* APLL : 1GHz */
>> +/* MCLK_CDREX: MCLK_CDREX_533*/
>> +/* LPDDR support: LPDDR2 */
>> +
>> +void mem_ctrl_asm_init()
>> +{
>> + struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
>> + struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
>> + struct exynos5_dmc *dmc;
>> + unsigned int val;
>> +
>> + phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
>> + phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
>> + dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
>> +
>> + /* Reset PHY Controllor: PHY_RESET[0] */
>> + writel(0x0, &clk->lpddr3phy_ctrl);
>> +
>> + sdelay(0x10000);
>> +
>> + /*set Read Latance and Burst Length for PHY0 and PHY1 */
>> + val = 0x408;
>> + writel(val, &phy0_ctrl->phy_con42);
>> + writel(val, &phy1_ctrl->phy_con42);
>> +
>> + /*
>> + * ZQ Calibration:
>> + * Select Driver Strength,
>> + * long calibration for manual calibration
>> + */
>> + val = 0x0DA40304;
>> + writel(val, &phy0_ctrl->phy_con16);
>> + writel(val, &phy1_ctrl->phy_con16);
>> +
>> + /* Enable termination */
>> + val = 0x0DAC0304;
>> + writel(val, &phy0_ctrl->phy_con16);
>> + writel(val, &phy1_ctrl->phy_con16);
>> +
>> + /* Start Manual Calibration */
>> + val = 0x0DAC0306;
>> + writel(val, &phy0_ctrl->phy_con16);
>> + writel(val, &phy1_ctrl->phy_con16);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Enable termination */
>> + val = 0x0DAC0304;
>> + writel(val, &phy0_ctrl->phy_con16);
>> + writel(val, &phy1_ctrl->phy_con16);
>> +
>> + /* DDR Mode: LPDDR2 */
>> + val = 0x17021240;
>> + writel(val, &phy0_ctrl->phy_con0);
>> + writel(val, &phy1_ctrl->phy_con0);
>> +
>> + /* DQS, DQ: Signal, for LPDDR2: Always Set */
>> + val = 0x00000F0F;
>> + writel(val, &phy0_ctrl->phy_con14);
>> + writel(val, &phy1_ctrl->phy_con14);
>> +
>> + /* RD_FETCH: 1 */
>> + val = 0x1FFF1000;
>> + writel(val, &dmc->concontrol);
>> + sdelay(0x10000);
>> +
>> + val = 0x0FFF1000;
>> + writel(val, &dmc->concontrol);
>> + sdelay(0x10000);
>> +
>> + /*
>> + * Update DLL Information:
>> + * Force DLL Resyncronization
>> + */
>> + val = 0x00000008;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /* Reset Force DLL Resyncronization */
>> + val = 0x00000000;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /*
>> + * Dynamic Clock: Always Running
>> + * Memory Burst length: 4
>> + * Number of chips: 2
>> + * Memory Bus width: 32 bit
>> + * Memory Type: LPDDR2-S4
>> + * Additional Latancy for PLL: 1 Cycle
>> + */
>> + val = 0x00212500;
>> + writel(val, &dmc->memcontrol);
>> +
>> + /*
>> + * Memory Configuration Chip 0
>> + * Address Mapping: Interleaved
>> + * Number of Column address Bits: 10 bits
>> + * Number of Rows Address Bits: 14
>> + * Number of Banks: 8
>> + */
>> + val = 0x00001323;
>> + writel(val, &dmc->memconfig0);
>> +
>> + /*
>> + * Memory Configuration Chip 1
>> + * Address Mapping: Interleaved
>> + * Number of Column address Bits: 10 bits
>> + * Number of Rows Address Bits: 14
>> + * Number of Banks: 8
>> + */
>> + val = 0x00001323;
>> + writel(val, &dmc->memconfig1);
>> +
>> + /*
>> + * Chip0: AXI
>> + * AXI Base Address: 0x40000000
>> + * AXI Base Address Mask: 0x780
>> + */
>> + val = 0x00400780;
>> + writel(val, &dmc->membaseconfig0);
>> +
>> + /*
>> + * Chip1: AXI
>> + * AXI Base Address: 0x80000000
>> + * AXI Base Address Mask: 0x780
>> + */
>> + val = 0x00800780;
>> + writel(val, &dmc->membaseconfig1);
>> +
>> + /* Precharge Configuration */
>> + val = 0xFF000000;
>> + writel(val, &dmc->prechconfig);
>> +
>> + /* Power Down mode Configuration */
>> + val = 0xFFFF00FF;
>> + writel(val, &dmc->pwrdnconfig);
>> +
>> + /* Periodic Refrese Interval */
>> + val = 0x0000005D;
>> + writel(val, &dmc->timingref);
>> +
>> + /* MCLK_CDREX_533 */
>> + /*
>> + * TimingRow, TimingData, TimingPower Setting:
>> + * Values as per Memory AC Parameters
>> + */
>> + val = 0x2336544C;
>> + writel(val, &dmc->timingrow);
>> +
>> + val = 0x24202408;
>> + writel(val, &dmc->timingdata);
>> +
>> + val = 0x38260235;
>> + writel(val, &dmc->timingpower);
>> +
>> + /* Memory Channel Inteleaving Size: 128 Bytes */
>> + val = CONFIG_IV_SIZE;
>> + writel(val, &dmc->ivcontrol);
>> +
>> + /* Set Offsets to read DQS */
>> + val = 0x7F7F7F7F;
>> + writel(val, &phy0_ctrl->phy_con4);
>> + writel(val, &phy1_ctrl->phy_con4);
>> +
>> + /* Set Offsets to read DQ */
>> + val = 0x7F7F7F7F;
>> + writel(val, &phy0_ctrl->phy_con6);
>> + writel(val, &phy1_ctrl->phy_con6);
>> +
>> + /* Debug Offset */
>> + val = 0x0000007F;
>> + writel(val, &phy0_ctrl->phy_con10);
>> + writel(val, &phy1_ctrl->phy_con10);
>> +
>> + /* Start DLL Locking */
>> + val = 0x10107F50;
>> + writel(val, &phy0_ctrl->phy_con12);
>> + writel(val, &phy1_ctrl->phy_con12);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * Update DLL Information:
>> + * Force DLL Resyncronization
>> + */
>> + val = 0x00000008;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /* Reset DLL Resyncronization */
>> + val = 0x00000000;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /*
>> + * NOP CMD: Channel 0, Chip 0
>> + * Exit from active/precharge power down or deep power down
>> + */
>> + val = 0x07000000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
>> + val = 0x00071C00;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x00010BFC;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* MCLK_CDREX_533 */
>> + val = 0x00000708;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x00000818;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * NOP CMD: Channel 0, Chip 1
>> + * Exit from active/precharge power down or deep power down
>> + */
>> + val = 0x07100000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
>> + val = 0x00171C00;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x00110BFC;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* MCLK_CDREX_533 */
>> + val = 0x00100708;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x00100818;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * NOP CMD: Channel 1, Chip 0
>> + * Exit from active/precharge power down or deep power down
>> + */
>> + val = 0x17000000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
>> + val = 0x10071C00;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x10010BFC;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* MCLK_CDREX_533 */
>> + val = 0x10000708;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x10000818;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * NOP CMD: Channel 1, Chip 1
>> + * Exit from active/precharge power down or deep power down
>> + */
>> + val = 0x17100000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
>> + val = 0x10171C00;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x10110BFC;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* MCLK_CDREX_533 */
>> + val = 0x10100708;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + val = 0x10100818;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Reset DQS Offsets */
>> + val = 0x08080808;
>> + writel(val, &phy0_ctrl->phy_con4);
>> + writel(val, &phy1_ctrl->phy_con4);
>> +
>> + /* Reset DQ Offsets */
>> + val = 0x08080808;
>> + writel(val, &phy0_ctrl->phy_con6);
>> + writel(val, &phy1_ctrl->phy_con6);
>> +
>> + /* Reset debug Offsets */
>> + val = 0x00000008;
>> + writel(val, &phy0_ctrl->phy_con10);
>> + writel(val, &phy1_ctrl->phy_con10);
>> +
>> + /* Set DLL Locking */
>> + val = 0x10107F30;
>> + writel(val, &phy0_ctrl->phy_con12);
>> + writel(val, &phy1_ctrl->phy_con12);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Start DLL Locking */
>> + val = 0x10107F70;
>> + writel(val, &phy0_ctrl->phy_con12);
>> + writel(val, &phy1_ctrl->phy_con12);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * Update DLL Information:
>> + * Force DLL Resyncronization
>> + */
>> + val = 0x00000008;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /* Reset DLL Resyncronization */
>> + val = 0x00000000;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + sdelay(0x10000);
>> +
>> + /*
>> + * Update DLL Information:
>> + * Force DLL Resyncronization
>> + */
>> + val = 0x00000008;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /* Reset DLL Resyncronization */
>> + val = 0x00000000;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + sdelay(0x10000);
>> +#if defined(CONFIG_RD_LVL)
>> + /* DLL On */
>> + val = 0x10102D50;
>> + writel(val, &phy0_ctrl->phy_con12);
>> + writel(val, &phy1_ctrl->phy_con12);
>> +
>> + /*
>> + * Set ctrl_gateadj, ctrl_readadj
>> + * ctrl_gateduradj, rdlvl_pass_adj
>> + * rdlvl_rddataPadj
>> + */
>> + val = 0x09210001;
>> + writel(val, &phy0_ctrl->phy_con1);
>> + writel(val, &phy1_ctrl->phy_con1);
>> +
>> + /* LPDDR2 Address */
>> + val = 0x00000208;
>> + writel(val, &phy0_ctrl->phy_con22);
>> + writel(val, &phy1_ctrl->phy_con22);
>> +
>> + /* Enable Byte Read Leleling */
>> + val = 0x17023240;
>> + writel(val, &phy0_ctrl->phy_con0);
>> + writel(val, &phy1_ctrl->phy_con0);
>> +
>> + /* rdlvl_en: Use levelling offset instead ctrl_shiftc */
>> + val = 0x02010004;
>> + writel(val, &phy0_ctrl->phy_con2);
>> + writel(val, &phy1_ctrl->phy_con2);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Enable Data Eye Trainig */
>> + val = 0x00000002;
>> + writel(val, &dmc->rdlvl_config);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Disable Data Eye Trainig */
>> + val = 0x00000000;
>> + writel(val, &dmc->rdlvl_config);
>> +
>> + /* RdDeSkew_clear: Clear */
>> + val = 0x02012004;
>> + writel(val, &phy0_ctrl->phy_con2);
>> + writel(val, &phy1_ctrl->phy_con2);
>> +
>> + /* Start DLL Locking */
>> + val = 0x10107F70;
>> + writel(val, &phy0_ctrl->phy_con12);
>> + writel(val, &phy1_ctrl->phy_con12);
>> +
>> + /* Force DLL Resyncronization */
>> + val = 0x00000008;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + /* Reset DLL Resyncronization */
>> + val = 0x00000000;
>> + writel(val, &dmc->phycontrol0);
>> +
>> + sdelay(0x10000);
>> +
>> + /* ctrl_atgate: ctrl_gate_p*, ctrl_read_p* generated by PHY*/
>> + val = 0x17023200;
>> + writel(val, &phy0_ctrl->phy_con0);
>> + writel(val, &phy1_ctrl->phy_con0);
>> +
>> + /* Channel:0, Chip:0, PALL (all banks precharge) CMD */
>> + val = 0x01000000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Channel:0, Chip:1, PALL (all banks precharge) CMD */
>> + val = 0x01100000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Channel:1, Chip:0, PALL (all banks precharge) CMD */
>> + val = 0x11000000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +
>> + /* Channel:1, Chip:1, PALL (all banks precharge) CMD */
>> + val = 0x11100000;
>> + writel(val, &dmc->directcmd);
>> +
>> + sdelay(0x10000);
>> +#endif
>> + /*
>> + * Dynamic Clock: Stops During Idle Period
>> + * Dynamic Power Down: Enable
>> + * Dynamic Self refresh: Enable
>> + * Memory Burst length: 4
>> + * Number of chips: 2
>> + * Memory Bus width: 32 bit
>> + * Memory Type: LPDDR2-S4
>> + * Additional Latancy for PLL: 1 Cycle
>> + */
>> + val = 0x00212523;
>> + writel(val, &dmc->memcontrol);
>> +
>> + /* Start Auto refresh */
>> + val = 0x0FFF10E0;
>> + writel(val, &dmc->concontrol);
>
> All those magic numbers above...
> Can't those be defined appropriately?
> Splitting the function to several functions would make it
> much more readable and nice (because currently it looks very ugly...).
> Are all these writes board specific?
I will submit a patch with proper defines and and modules shortly,
>
> [...]
>
>> diff --git a/board/samsung/smdk5250/smdk5250.c
>> b/board/samsung/smdk5250/smdk5250.c
>> new file mode 100644
>> index 0000000..66d56ab
>> --- /dev/null
>> +++ b/board/samsung/smdk5250/smdk5250.c
>> @@ -0,0 +1,152 @@
>> +/*
>> + * Copyright (C) 2011 Samsung Electronics
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <netdev.h>
>> +#include <asm/arch/cpu.h>
>> +#include <asm/arch/gpio.h>
>> +#include <asm/arch/mmc.h>
>> +#include <asm/arch/sromc.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +struct exynos5_gpio_part1 *gpio1;
>> +
>> +int board_init(void)
>> +{
>> + gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
>> +
>> + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
>> + return 0;
>> +}
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
>> + + get_ram_size((long *)PHYS_SDRAM_8,
>> PHYS_SDRAM_8_SIZE);
>> + return 0;
>> +}
>> +
>> +void dram_init_banksize(void)
>> +{
>> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
>> + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
>> + PHYS_SDRAM_1_SIZE);
>> + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
>> + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
>> + PHYS_SDRAM_2_SIZE);
>> + gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
>> + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
>> + PHYS_SDRAM_3_SIZE);
>> + gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
>> + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
>> + PHYS_SDRAM_4_SIZE);
>> + gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
>> + gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5, \
>> + PHYS_SDRAM_5_SIZE);
>> + gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
>> + gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6, \
>> + PHYS_SDRAM_6_SIZE);
>> + gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
>> + gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7, \
>> + PHYS_SDRAM_7_SIZE);
>> + gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
>> + gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8, \
>> + PHYS_SDRAM_8_SIZE);
>
> No need for the back slashes...
Yes will remove them.
>
> [...]
>
>> diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
>> new file mode 100644
>> index 0000000..194130d
>> --- /dev/null
>> +++ b/include/configs/smdk5250.h
>> @@ -0,0 +1,198 @@
>> +/*
>> + * Copyright (C) 2011 Samsung Electronics
>> + *
>> + * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +/* High Level Configuration Options */
>> +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
>> +#define CONFIG_S5P 1 /* S5P Family */
>> +#define CONFIG_EXYNOS5 1 /* which is in a Exynos5
>> Family */
>> +#define CONFIG_CPU_EXYNOS5250 1 /* which is in a Exynos5250 */
>> +#define CONFIG_SMDK5250 1 /* which is in a SMDK5250 */
>
> Boolean defines should not have a value. Please, fix globally...
Sure
>
>> +
>> +#include <asm/arch/cpu.h> /* get chip and board defs */
>> +
>> +#define CONFIG_ARCH_CPU_INIT
>> +#define CONFIG_DISPLAY_CPUINFO
>> +#define CONFIG_DISPLAY_BOARDINFO
>> +
>> +/* Keep L2 Cache Disabled */
>> +#define CONFIG_L2_OFF 1
>> +#define CONFIG_SYS_DCACHE_OFF 1
>> +
>> +#define CONFIG_SYS_SDRAM_BASE 0x40000000
>> +#define CONFIG_SYS_TEXT_BASE 0x43E00000
>> +
>> +/* input clock of PLL: SMDK5250 has 24MHz input clock */
>> +#define CONFIG_SYS_CLK_FREQ 24000000
>> +
>> +#define CONFIG_SETUP_MEMORY_TAGS
>> +#define CONFIG_CMDLINE_TAG
>> +#define CONFIG_INITRD_TAG
>> +#define CONFIG_CMDLINE_EDITING
>> +
>> +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
>> +#define MACH_TYPE_SMDK5250 3774
>> +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
>> +
>> +/* Power Down Modes */
>> +#define S5P_CHECK_SLEEP 0x00000BAD
>> +#define S5P_CHECK_DIDLE 0xBAD00000
>> +#define S5P_CHECK_LPA 0xABAD0000
>> +
>> +/* Offset for inform registers */
>> +#define INFORM0_OFFSET 0x800
>> +#define INFORM1_OFFSET 0x804
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
>> +
>> +/* select serial console configuration */
>> +#define CONFIG_SERIAL_MULTI 1
>> +#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
>> +#define CONFIG_BAUDRATE 115200
>> +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
>> +
>> +#define TZPC_BASE_OFFSET 0x10000
>> +
>> +/* SD/MMC configuration */
>> +#define CONFIG_GENERIC_MMC 1
>> +#define CONFIG_MMC 1
>> +#define CONFIG_S5P_MMC 1
>> +
>> +#define CONFIG_BOARD_EARLY_INIT_F
>> +
>> +/* PWM */
>> +#define CONFIG_PWM 1
>> +
>> +/* allow to overwrite serial and ethaddr */
>> +#define CONFIG_ENV_OVERWRITE
>> +
>> +/* Command definition*/
>> +#include <config_cmd_default.h>
>> +
>> +#define CONFIG_CMD_PING
>> +#define CONFIG_CMD_ELF
>> +#define CONFIG_CMD_MMC
>> +#define CONFIG_CMD_EXT2
>> +#define CONFIG_CMD_FAT
>> +#undef CONFIG_CMD_NET
>> +#undef CONFIG_CMD_NFS
>> +
>> +#define CONFIG_BOOTDELAY 3
>> +#define CONFIG_ZERO_BOOTDELAY_CHECK
>> +
>> +#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
>> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser
>> */
>> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
>> +#define CONFIG_SYS_PROMPT "SMDK5250 # "
>> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
>> +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
>> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args
>> */
>> +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
>> +/* Boot Argument Buffer Size */
>> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>> +/* memtest works on */
>> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
>> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE +
>> 0x5E00000)
>> +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
>> +
>> +#define CONFIG_SYS_HZ 1000
>> +
>> +/* valid baudrates */
>> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
>> +
>> +/* Stack sizes */
>> +#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
>> +
>> +#define CONFIG_NR_DRAM_BANKS 8
>> +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
>> +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
>> +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
>> +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
>> +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
>> +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
>> +
>> +#define CONFIG_SYS_MONITOR_BASE 0x00000000
>> +
>> +/* (Memory Interleaving Size = 1 << IV_SIZE) */
>> +#define CONFIG_IV_SIZE 0x07
>> +#define CONFIG_RD_LVL 1
>> +
>> +/* FLASH and environment organization */
>> +#define CONFIG_SYS_NO_FLASH 1
>> +#undef CONFIG_CMD_IMLS
>> +#define CONFIG_IDENT_STRING " for SMDK5250"
>> +
>> +#define CONFIG_ENV_IS_IN_MMC 1
>> +#define CONFIG_SYS_MMC_ENV_DEV 0
>> +
>> +#define CONFIG_SECURE_BL1_ONLY
>> +
>> +/* Secure FW size configuration */
>> +#ifdef CONFIG_SECURE_BL1_ONLY
>> +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
>> +#else
>> +#define CONFIG_SEC_FW_SIZE 0
>> +#endif
>> +
>> +/* Configuration of BL1, BL2, ENV Blocks on mmc */
>> +#define CONFIG_RES_BLOCK_SIZE (512)
>> +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
>> +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
>> +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
>> +
>> +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
>> +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
>> +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
>> +
>> +/* U-boot copy size from boot Media to DRAM.*/
>> +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
>> +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
>> +#define CONFIG_DOS_PARTITION 1
>> +
>> +#define CONFIG_IRAM_STACK 0x02050000
>> +
>> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
>> +#define MMC_MAX_CHANNEL 5
>> +
>> +/* Enable devicetree support */
>> +#define CONFIG_OF_LIBFDT
>> +
>> +#endif /* __CONFIG_H */
>
> --
> Regards,
> Igor.
--
with warm regards,
Chander Kashyap
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