On Fri, 2011-09-16 at 11:30 +0200, Bianconi, Cyril wrote: > I don't think that the A9 issue is the same as the A8. However, > effects are the same i.e. it's hard to use PMU. > > I cannot communicate the A9 errata document as-is due to legal stuff > but I belive that I can explain the issue. > The issue happens when counters are in overflow (then not sure that > this impacts OProfile).
Overflow is the only way of getting a counter interrupt right? Then it's a fundamental problem for oprofile. > Theoritically, an interrupt should fire in this case. In reality, this > interrupt is lost randomly. > The ARM proposed workaround is to use 2 counters: counter 0 and > counter1 initialized at counter0+1. If one interrupt is lost, the > other one should fire just after. > We have noticed that this could not be sufficient and that a third > counter should be used to have close to 0% of the interrupts lost. So, even with three counters there's still a statistical chance of failure? > Note: This HW issue has been fixed by ARM quite "late", so I think > that most of the devices on the market should be impacted. Are there part numbers that we can be reasonably sure do work, say perhaps the 4460? Thanks, -dl
_______________________________________________ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
