On Fri, 19 Aug 2011 21:21:27 +0200, Per Forlin <per.for...@linaro.org>
wrote:
FSG_NUM_BUFFERS is set to 2 as default.
Usually 2 buffers are enough to establish a good buffering pipeline.
The number may be increased in order to compensate a for bursty VFS
behaviour.
Here follows a description of system that may require more than
2 buffers.
* CPU ondemand governor active
* latency cost for wake up and/or frequency change
* DMA for IO
Use case description.
* Data transfer from MMC via VFS to USB.
* DMA shuffles data from MMC and to USB.
* The CPU wakes up every now and then to pass data in and out from VFS,
which cause the bursty VFS behaviour.
Signed-off-by: Per Forlin <per.for...@linaro.org>
Acked-by: Michal Nazarewicz <min...@mina86.com>
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