On Tue, Feb 8, 2011 at 6:50 PM, Rob Herring <robherri...@gmail.com> wrote:
> On 02/08/2011 09:51 AM, Yong Shen wrote: > >> Hi Arnaud, >> >> I also took a while to think about this before posting patches. I prefer >> to put it in board related code since the various PMIC used on each >> boards may have influence on cpuidle latency or other charactors, >> although it could be minor. >> >> > But you are not going to be doing voltage scaling in idle. Is it even > possible to do sleeping operations like accessing a PMIC in idle? > I guess you are asking if modes like 'state retention' are possible for idle state. so far there is no official mapping between c-states and various arm idle states, which is something linaro power management group is working on. Therefore I also treat 'state retention' as a c-state. ps. remove lpdk in cc list to avoid auto-reply messages. Yong > > The core is powergated, so lowering voltage would not help. Doing bus > scaling or DDR self-refresh are the only likely additional operations. > > Rob >
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