Jon > -----Original Message----- > From: linaro-dev-boun...@lists.linaro.org [mailto:linaro-dev- > boun...@lists.linaro.org] On Behalf Of Jon Callan > Sent: Tuesday, October 12, 2010 4:10 PM > To: linaro-dev@lists.linaro.org > Subject: Common ARM context save/restore code > > Vishwa, > > I have a more-or-less complete set of example code for CPU context > save/restore, currently supporting A5/A8/A9 and with planned support for > Eagle. > > It is structured as "firmware" at the moment, but it would be much better > if it was integrated into the ARM Linux kernel. The idea is the kernel > calls it from CPUidle, and it saves all CPU context and cuts the power. > Then when power returns, it restores all CPU context and returns to the > kernel as if nothing has happened. > > It handles just the CPU and cluster context, which on A9mpcore includes > MMU, GIC, VFP, SCU, L2cc, Debug, etc. It takes care of cleaning caches and > entering/leaving the coherency domain. There is also support for TrustZone, > but as you say that's quite platform-specific. > This is something very different from SOC point of view. Example OMAP4, the restore for GIC, SCU, L2 is handled by ROM code and it expect it to save in a particular pattern and pre-defined memory location. Generic code won't work here.
VFP save/restore isn't needed because the generic code already takes care of it. Infact on OMAP4 I need to save/restore only 14 CP15 registers (only needed ones) to get things working. Rest all is handles as mentioned using secure code. Having said that, would be good to see your patches. Regards, Santosh _______________________________________________ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
