Matthew Lai <m...@matthewlai.ca> wrote:
> Code:
>
> ---------------------------------------------------------------------
>
> #include <libopencm3/stm32/rcc.h>
> #include <libopencm3/stm32/timer.h>
>
> int main(void)
> {
> rcc_periph_clock_enable(RCC_TIM3);
> timer_set_period(TIM3, 1);
> return 0;
> }
>
> ---------------------------------------------------------------------
>
> Using default compiler options for f4:
>
> ---------------------------------------------------------------------
>
> 080001ac <main>:
> 80001ac: b508 push {r3, lr}
> 80001ae: f640 0001 movw r0, #2049 ; 0x801
> 80001b2: f000 f80b bl 80001cc <rcc_periph_clock_enable>
> 80001b6: 2101 movs r1, #1
> 80001b8: 4802 ldr r0, [pc, #8] ; (80001c4 <main+0x18>)
> 80001ba: f000 f805 bl 80001c8 <timer_set_period>
> 80001be: 2000 movs r0, #0
> 80001c0: bd08 pop {r3, pc}
> 80001c2: bf00 nop
> 80001c4: 40000400 .word 0x40000400
>
> 080001c8 <timer_set_period>:
> 80001c8: 62c1 str r1, [r0, #44] ; 0x2c
> 80001ca: 4770 bx lr
>
> 080001cc <rcc_periph_clock_enable>:
> 80001cc: 0943 lsrs r3, r0, #5
> 80001ce: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000
> 80001d2: f503 330e add.w r3, r3, #145408 ; 0x23800
> 80001d6: f000 021f and.w r2, r0, #31
> 80001da: 6819 ldr r1, [r3, #0]
> 80001dc: 2001 movs r0, #1
> 80001de: 4090 lsls r0, r2
> 80001e0: 4308 orrs r0, r1
> 80001e2: 6018 str r0, [r3, #0]
> 80001e4: 4770 bx lr
>
> ---------------------------------------------------------------------
>
> The store in rcc_periph_clock_enable happens at 80001e2. After
> returning to main(), we take 2 cycles to load arguments to
> timer_set_period, then calls it, and timer_set_period writes to
> the timer register in the first instruction.
>
> If my math is correct, the second write happens on the 5th
> cycle after the first write. This violates the errata sheet
> constraint by one cycle. For APB peripherals, the errata sheet
> says we need to wait 1 + (AHB/APB) cycles, which in this case
> would be 5 (most people use (AHB/APB = 4).
>
> Now this is with default compiler options on f4, with the
> lowest APB prescaler. With a higher prescaler, it would be even
> worse. With -flto, it would be even worse. On f7, we are very
> very far from the 8 cycles required (keeping in mind that
> Cortex-M7 can execute 2 instructions per cycle).
>
> So I believe we are hitting it on all series (that require this
> delay), at default compiler settings and clock settings
> provided by libopencm3.So, you should be able to configure the timer to actually output something, and otuput at the wrong speed because a write was too early right?
signature.html
Description: OpenPGP Digital Signature
------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________ libopencm3-devel mailing list libopencm3-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
