What I do Warren is have the USART read into a FIFO, so the ISR just
takes characters as they arrive and sticks then in a fifo and updates
the index of where to stick the next character. The read function has
its own index and just reads from the FIFO when the current and next
index differ. A check for a character available is simply if
(cur_index != next_index)
--Chuck
On Mon, Feb 20, 2017 at 9:21 AM, Warren Gay <ve3...@gmail.com> wrote:
> I am using FreeRTOS in connection with libopencm3. Within a task however, I
> would like to be able to query the TX or RX status prior to committing to a
> blocking operation. However, libopencm3() only provides blocking operations,
> which spin on the CPU.
>
> The following code gives the spirit of what I am trying to do:
>
> inline static int
> usart_tx_ready(uint32_t usart) {
> return (USART_SR(usart) & USART_SR_TXE) != 0;
> }
>
> static void
> uart_task(void *args) {
> char ch;
>
> for (;;) {
> /* Receive char to be TX */
> if ( xQueueReceive(uart_txq,&ch,500) == pdPASS ) {
> while ( !usart_tx_ready(USART1) )
> taskYIELD(); /* Yield CPU to ready tasks */
> usart_send_blocking(USART1,ch); /* blocking call */
> }
> }
> }
>
> The present code has the appearance of working but using the UART register
> directly (is there a potential ISR conflict with this?)
>
> Eventually, I'll want to do something similar for receiving. Ideally, this
> would allow one thread (task) to handle both the RX and TX, to avoid thread
> related problems.
>
> So it would be a welcome addition to the libopencm3 library to provide
> routines:
>
> int usart_send_ready(uint32_t usart);
> int usart_recv_ready(uint32_t usart);
>
> Is there any interest in this? If not, is the approach used for TX above
> valid? Will the same approach be safe for RX? I didn't look to see if the
> recv side was interrupt driven or not.
>
> Thanks, Warren
>
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