The cns3xxx interrupt controller uses a single register and as such
the 'mask' reg/functions must be used as opposed to the 'enable'/'disable'
reg/functions.
This fixes an issue that occurs if more than one GPIO on a specific controller
(there is GPIOA and GPIOB each having 32 GPIO's) uses interrupts. When one
would get enabled all others would be disabled prior to this patch.
Signed-off-by: Tim Harvey <thar...@gateworks.com>
---
target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
index 19de24c..bdf930a 100644
--- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
+++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c
@@ -273,10 +273,10 @@ void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
ct = gc->chip_types;
ct->type = IRQ_TYPE_EDGE_FALLING;
ct->regs.ack = GPIO_INTERRUPT_CLEAR;
- ct->regs.enable = GPIO_INTERRUPT_ENABLE;
ct->chip.irq_ack = irq_gc_ack_set_bit;
- ct->chip.irq_enable = irq_gc_unmask_enable_reg;
- ct->chip.irq_disable = irq_gc_mask_disable_reg;
+ ct->regs.mask = GPIO_INTERRUPT_ENABLE;
+ ct->chip.irq_enable = irq_gc_mask_set_bit;
+ ct->chip.irq_disable = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
ct->handler = handle_edge_irq;
--
2.7.4
_______________________________________________
Lede-dev mailing list
Lede-dev@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/lede-dev
