On 02/05/2014 01:54 PM, Hans-Peter Diettrich wrote:
Please note that even a CPU with multiple cores doesn't have multiple
data busses for the cores. That's the narrowest bottleneck, which
limits the throughput on every standard machine.
Right, But this is why 1st Level cache has been invented :-) , (and why
expensive multicore chips have more cache than cheaper ones).
-Michael
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