On Wed, Jun 29, 2011 at 10:04 AM, Michael Schnell <[email protected]> wrote: > But correct Posix compliant code is supposed to work on hardware with any > count of cores. So there seems to be a bug _somewhere_.
>From what I observed and read, using Interlocked assignments or Compare and Swap was designed to explicitly resolve the issue of stale core cache values and even code execution with regard to such assignments. I don't see anything in POSIX documentation that explicitly ties execution order and core cache - as this is low level as it gets. It should be noted that core switching is done so without application awareness. I would love nothing more than to be able to have critical section force a "core lock" but I think this goes well beyond the scope of the engineering intention of CrticialSections. -- _______________________________________________ Lazarus mailing list [email protected] http://lists.lazarus.freepascal.org/mailman/listinfo/lazarus
