For Guest accessible SPRGs 4-7, save/restore must be handled differently for
64bit and
non-64 bit case. The registers are maintained as 64 bit copies by KVM. While
saving/restoring
for the non-64 bit case we should always take the lower 4 bytes.
Signed-off-by: Varun Sethi <varun.se...@freescale.com>
---
arch/powerpc/kvm/bookehv_interrupts.S | 48 +++++++++++++++++++++++++++-----
1 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S
b/arch/powerpc/kvm/bookehv_interrupts.S
index 909e96e..c1c0bae 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -320,13 +320,29 @@ _GLOBAL(kvmppc_resume_host)
PPC_STL r5, VCPU_LR(r4)
mfspr r7, SPRN_SPRG5
PPC_STL r3, VCPU_VRSAVE(r4)
- PPC_STL r6, VCPU_SHARED_SPRG4(r11)
+#ifdef CONFIG_64BIT
+ std r6, VCPU_SHARED_SPRG4(r11)
+#else
+ stw r6, (VCPU_SHARED_SPRG4 + 4)(r11)
+#endif
mfspr r8, SPRN_SPRG6
- PPC_STL r7, VCPU_SHARED_SPRG5(r11)
+#ifdef CONFIG_64BIT
+ std r7, VCPU_SHARED_SPRG5(r11)
+#else
+ stw r7, (VCPU_SHARED_SPRG5 + 4)(r11)
+#endif
mfspr r9, SPRN_SPRG7
- PPC_STL r8, VCPU_SHARED_SPRG6(r11)
+#ifdef CONFIG_64BIT
+ std r8, VCPU_SHARED_SPRG6(r11)
+#else
+ stw r8, (VCPU_SHARED_SPRG6 + 4)(r11)
+#endif
mfxer r3
- PPC_STL r9, VCPU_SHARED_SPRG7(r11)
+#ifdef CONFIG_64BIT
+ std r9, VCPU_SHARED_SPRG7(r11)
+#else
+ stw r9, (VCPU_SHARED_SPRG7 + 4)(r11)
+#endif
/* save guest MAS registers and restore host mas4 & mas6 */
mfspr r5, SPRN_MAS0
@@ -549,13 +565,29 @@ lightweight_exit:
* SPRGs, so we need to reload them here with the guest's values.
*/
lwz r3, VCPU_VRSAVE(r4)
- lwz r5, VCPU_SHARED_SPRG4(r11)
+#ifdef CONFIG_64BIT
+ ld r5, VCPU_SHARED_SPRG4(r11)
+#else
+ lwz r5, (VCPU_SHARED_SPRG4 + 4)(r11)
+#endif
mtspr SPRN_VRSAVE, r3
- lwz r6, VCPU_SHARED_SPRG5(r11)
+#ifdef CONFIG_64BIT
+ ld r6, VCPU_SHARED_SPRG5(r11)
+#else
+ lwz r6, (VCPU_SHARED_SPRG5 + 4)(r11)
+#endif
mtspr SPRN_SPRG4W, r5
- lwz r7, VCPU_SHARED_SPRG6(r11)
+#ifdef CONFIG_64BIT
+ ld r7, VCPU_SHARED_SPRG6(r11)
+#else
+ lwz r7, (VCPU_SHARED_SPRG6 + 4)(r11)
+#endif
mtspr SPRN_SPRG5W, r6
- lwz r8, VCPU_SHARED_SPRG7(r11)
+#ifdef CONFIG_64BIT
+ ld r8, VCPU_SHARED_SPRG7(r11)
+#else
+ lwz r8, (VCPU_SHARED_SPRG7 + 4)(r11)
+#endif
mtspr SPRN_SPRG6W, r7
mtspr SPRN_SPRG7W, r8
--
1.7.2.2
--
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