Michael S. Tsirkin wrote:
Here's the race as I see it: we discussed the possibility of making kernel and user share and actual memory page, and using that for MSI-X tables.host kernel want to send msi x message host kernel test mask bit: unmasked guest sets mask bit guest does read to flash msi writes guest does sync irq and makes sure there are no outstanging interrupts ---> at this stage guest expects not to get interrupts guest starts editing msix entry host kernel never saw mask so it sends message to the old address or even a corrupted address which the guest is in the middle of editing bad things happen This race is not easy to solve, except by catching writes to msix table, and syncronising them with interrupt delivery.
You're right of course. In any case this is premature, we'll have to see if this happens with any frequency.
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