On 01/09/2015 04:44 PM, Kai Huang wrote:
When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding TLB entity in the hardware won't be updated immediately. We should flush it to guarantee the consistence of D bit between TLB and MMU page table in memory. This is required if some specific hardware feature uses D-bit status to do specific things.
Currently, A/D is lazied synced and it does not hurt anything since we have marked the page dirty after clearing the bit and mmu-notifier can keep the coherence on host (It is the guest's responsibility to sync TLBs when changing the bit). So, i am just curious what "some specific hardware" is. :) -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
