2014-09-30 20:49+0300, Nadav Amit:
> Intel SDM 17.2.4 (Debug Control Register (DR7)) says: "The processor clears
> the
> GD flag upon entering to the debug exception handler." This sentence may be
> misunderstood as if it happens only on #DB due to debug-register protection,
> but it happens regardless to the cause of the #DB.
All real hardware behaves that way?
Intel has another sentence after that
[...], to allow the handler access to the debug registers.
I suppose that the "the" is important, but I haven't verified it.[1]
Clearing GD on every #DB would also make the stated purpose[2] harder to
achieve without adding any benefit; it seems like a bug for Intel.
---
1: AMD [13.1.1.4 Debug-Control Register (DR7)] uses a similar wording
General-Detect Enable (GD)—Bit 13. Software sets this bit to 1 to
cause a debug exception to occur when an attempt is made to execute
a MOV DRn instruction to any debug register (DR0–DR7). This bit is
cleared to 0 by the processor when the #DB handler is entered,
allowing the handler to read and write the DRn registers. The #DB
exception occurs before executing the instruction, and DR6[BD] is
set by the processor. Software debuggers can use this bit to
prevent the currently-executing program from interfering with the
debug operation.
2: Last sentence of [1] and also this from Intel
This condition is provided to support in-circuit emulators.
When the emulator needs to access the debug registers, emulator
software can set the GD flag to prevent interference from the
program currently executing on the processor.
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