André, Please give us an example where you would need to connect more than 2 nets. I understand perfectly the net tie for connecting Analog Ground to digital ground somewhere in a PCB, but I have hard time to figure out a case where you would need more then 2 nets. For AGND to DGND, a simple 0 ohm resistor will do the trick, and can be used with a resistor, a capacitor, a diode or an inductor without being a nuisance and no worries about DRC.
My two cents, Jean-Paul N1JPL > On Apr 22, 2016, at 11:34 AM, André S. <list.dev.ki...@nospamail.de> wrote: > > > > Hi everyone, > > From a users view I also would love to use net ties in Kicad. > In my opinion they should allow to connect 2 to 4 nets on one point. > In the schematic they could be just a normal component from the presentation > and handling. They may just need a custom field to identify as a net tie. > > In Pcbnew they need a special handling in my opinion. > In general on a multilayer board one should aim for a solid ground layer. > However in the logical (schematic) representation it is good practice to > separate analog and digital circuits. So you end up with a digital ground and > an analog ground net that need to meet at one location on the board (e.g. at > an ADC). > But this connection should be not limited to a single point but more of a > meeting area. > Therefore one would need some means of allowing overlapping of these nets > connected with a net tie and also raising a DRC error if the nets are not > connected. Maybe a special "net connector" is required that is member of both > nets? > > Just my thoughts on this. > > > Regards, > André > > > On April 22, 2016 3:23:12 PM GMT+02:00, Tomasz Wlostowski > <tomasz.wlostow...@cern.ch> wrote: >> On 22.04.2016 15:11, Chris Pavlina wrote: >>> You've never seen an EDA package support net ties? Or seen them used >> to >>> separate logical power planes? Quite common, really... >> >> Me too. >> >> IMHO it can be done without any changes on the eeschema side by adding >> a >> special component to the standard library (just like GND/power ports). >> PCBnew could interpret it as a zero-sized copper pad. Some DRC >> modifications would be needed to correctly take into account clearances >> of the nets connected by a tie. >> >> Tom >>> >>> I'd _love_ to see proper net tie support in KiCad. :) >>> >>> On Fri, Apr 22, 2016 at 09:04:10AM -0400, Wayne Stambaugh wrote: >>>> On 4/20/2016 4:00 PM, Simon Richter wrote: >>>>> Hi, >>>>> >>>>> as wxWidgets is getting on my nerves with editing widgets in the >> pin >>>>> table not rendering properly, I've started on support for net ties. >>>>> >>>>> In the current iteration, they would be placed the same way as >> junctions. >>>>> >>>>> Rules: >>>>> >>>>> - Any wire or pin connected to a net tie is in a separate net >> (unless >>>>> connected elsewhere). >>>>> - The net tie maps to a pseudo-pad that all three nets need to be >>>>> connected to. >>>>> - Connecting the nets there does not give a DRC error -- anywhere >> else >>>>> will. >>>>> - The pseudo-pad can be placed on a regular pad if it is on one of >> the >>>>> nets connected to the net tie. >>>>> >>>>> Use cases: >>>>> >>>>> - Analog and digital supply planes connected with a trace, but >>>>> otherwise separate >>>> >>>> I'm going to put my EE hat on and say that if you connect two power >>>> planes with a trace then they are the same plane no matter what you >>>> called them in your schematic. A more typical solution in this case >>>> would be to physically separate them by some type of component or >>>> components. Usually inductors or 0 ohm resistors (aka jumpers) are >> used >>>> in this situation depending on what you are trying to accomplish. >>>> >>>>> - Current sense resistors between a supply rail and a load >>>>> - Decoupling capacitors. >>>> >>>> I can see the decoupling capacitor use case where you want to tie a >> cap >>>> to a specific component power pin. >>>> >>>>> >>>>> I've added UI[1] and save support in eeschema already, still needs >>>>> mapping to the netlist and pcbnew support. >>>> >>>> Are you aware that changes to the current schematic file format are >>>> forbidden until we (I) finish implementing the new file format? >> This >>>> was discussed fairly recently so everyone should be aware of this. >> In >>>> any event, you should have gotten input from the development team >> before >>>> heading down this path. This is good advice for any developer. >> Even I >>>> solicit input on new features or large changes because other devs >> always >>>> seem to think of things I didn't. >>>> >>>> I don't have a strong opinion one way or the other about this >> feature. >>>> On the surface it does seem useful but I've never seen any EDA >> product >>>> support this so board designers may not understand why they would >> want >>>> to use it. Any one else have any thoughts on this? You may also >> want >>>> to check with the users to see if it's something that they would >> even use. >>>> >>>>> >>>>> There doesn't appear to be a real standard on how to represent net >> ties >>>>> in the schematic, though. A design note[2] from Linear Technologies >> uses >>>>> 45 degree angles on wires to make it look really intentional that >> the >>>>> wires should meet in the same spot, but that would be a major >> hassle >>>>> both to implement and use. >>>>> >>>>> For now I've gone with a larger dot, but that is very unintuitive. >>>>> Printing net names next to wires is difficult, because these are >> still >>>>> wires only. Numbers next to the wires might be doable, but >> confusing, so >>>>> if anyone has a good idea how to represent them, please speak up. >>>> >>>> How about a different color dot or a different shape. A different >> shape >>>> may be better for users who are color blind. >>>> >>>>> >>>>> Simon >>>>> >>>>> [1] http://psi5.com/~geier/net-tie.ogv >>>>> [2] http://cds.linear.com/docs/en/design-note/dn434f.pdf >>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> Mailing list: https://launchpad.net/~kicad-developers >>>>> Post to : kicad-developers@lists.launchpad.net >>>>> Unsubscribe : https://launchpad.net/~kicad-developers >>>>> More help : https://help.launchpad.net/ListHelp >>>>> >>>> >>>> >>>> _______________________________________________ >>>> Mailing list: https://launchpad.net/~kicad-developers >>>> Post to : kicad-developers@lists.launchpad.net >>>> Unsubscribe : https://launchpad.net/~kicad-developers >>>> More help : https://help.launchpad.net/ListHelp >>> >>> _______________________________________________ >>> Mailing list: https://launchpad.net/~kicad-developers >>> Post to : kicad-developers@lists.launchpad.net >>> Unsubscribe : https://launchpad.net/~kicad-developers >>> More help : https://help.launchpad.net/ListHelp >>> >> >> >> _______________________________________________ >> Mailing list: https://launchpad.net/~kicad-developers >> Post to : kicad-developers@lists.launchpad.net >> Unsubscribe : https://launchpad.net/~kicad-developers >> More help : https://help.launchpad.net/ListHelp > > > _______________________________________________ > Mailing list: https://launchpad.net/~kicad-developers > Post to : kicad-developers@lists.launchpad.net > Unsubscribe : https://launchpad.net/~kicad-developers > More help : https://help.launchpad.net/ListHelp _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : kicad-developers@lists.launchpad.net Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
