https://bugs.kde.org/show_bug.cgi?id=445415
Bug ID: 445415
Summary: arm64 front end: alignment checks missing for atomic
instructions
Product: valgrind
Version: unspecified
Platform: Other
OS: Linux
Status: REPORTED
Severity: normal
Priority: NOR
Component: vex
Assignee: jsew...@acm.org
Reporter: jsew...@acm.org
Target Milestone: ---
For the arm64 front end, none of the atomic instructions have address
alignment checks included in their IR. They all should. The effect of
missing alignment checks in the IR is that, since this IR will in most cases
translated back to atomic instructions in the back end, we will get
alignment traps (SIGBUS) on the host side and not on the guest side,
which is (very) incorrect behaviour of the simulation.
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