https://bugs.kde.org/show_bug.cgi?id=434296
Julian Seward <jsew...@acm.org> changed:
What |Removed |Added
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CC| |jsew...@acm.org
--- Comment #3 from Julian Seward <jsew...@acm.org> ---
>From an implementation view this all looks fine. I have only the
minor query:
- /* Check for specification exception */
- vassert(m3 < 3);
- vassert((m5 & 0b1110) == 0);
+ s390_insn_assert("vistr", m3 < 3 && m5 == (m5 & 1));
Is it possible for any incoming instruction to cause this assertion to fail?
If so that should be reported as SIGILL, and not cause an assertion failure.
>From the code-expansion point of view, I am somewhat concerned that this
may cause failures in VEX due to generating too many instructions in the
back end, etc. But I can't think of any obvious improvement and it's clear
you've spent time thinking about this too.
The one thing I would suggest is that, for the instructions in question, in
the front end, set the returned DisResult::hint field to Dis_HintVerbose.
This tells the top level block-disassembly logic that the instruction just
translated to IR is "verbose" and so will cause it to stop pulling new insns
into the block sooner rather than later. For examples look for
dres->hint = Dis_HintVerbose;
in guest_amd64_toIR.c.
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