https://bugs.kde.org/show_bug.cgi?id=425232
Carl Love <c...@us.ibm.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|REPORTED |RESOLVED Resolution|--- |FIXED --- Comment #35 from Carl Love <c...@us.ibm.com> --- Patch set committed commit e3d32554219b53481fe91c68a756e63e62925e92 (origin/master, origin/HEAD) Author: Carl Love <c...@us.ibm.com> Date: Tue Oct 6 11:52:34 2020 -0500 Vector Integer Multiply/Divide/Modulo Instruction tests commit 78e7de504c9e311a15c3d081cc2098c568dc8399 Author: Carl Love <c...@us.ibm.com> Date: Tue Oct 6 11:51:19 2020 -0500 VSX 32-byte storage access operations commit 5fcffeabebc31df0e34099bec431be166ad0c44f Author: Carl Love <c...@us.ibm.com> Date: Tue Oct 6 11:44:50 2020 -0500 Set boolean support tests commit ba7b3343619b72d1b963926f0b89c25fca3d360f Author: Carl Love <c...@us.ibm.com> Date: Tue Oct 6 11:41:04 2020 -0500 Add byte reverse tests ; cleanups to foundation patch. commit 02b6a1de06e99ead310e91aa59ae1261aebaa761 Author: Carl Love <c...@us.ibm.com> Date: Wed May 13 15:19:07 2020 -0500 Add ISA 3.1 Vector Integer Multiply/Divide/Modulo Instructions Add support for: vdivesd Vector Divide Extended Signed Doubleword vdivesw Vector Divide Extended Signed Word vdiveud Vector Divide Extended Unsigned Doubleword vdiveuw Vector Divide Extended Unsigned Word vdivsd Vector Divide Signed Doubleword vdivsw Vector Divide Signed Word vdivud Vector Divide Unsigned Doubleword vdivuw Vector Divide Unsigned Word vmodsd Vector Modulo Signed Doubleword vmodsw Vector Modulo Signed Word vmodud Vector Modulo Unsigned Doubleword vmoduw Vector Modulo Unsigned Word vmulhsd Vector Multiply High Signed Doubleword vmulhsw Vector Multiply High Signed Word vmulhud Vector Multiply High Unsigned Doubleword vmulhuw Vector Multiply High Unsigned Word vmulld Vector Multiply Low Doubleword commit 34d142fffbec096a30b265f9e2cf277adb7d5c5c Author: Will Schmidt <will_schm...@vnet.ibm.com> Date: Mon Jun 22 09:57:21 2020 -0500 Add ISA 3.1 VSX 32-byte Storage Access Operations Add support for the new ISA 3.1 load and store instructions: lxvpx Load VSX Vector Paired Indexed plxvp Prefixed Load VSX Vector Paired pstxvp Prefixed Store VSX Vector Paired stxvpx Store VSX Vector Paired Indexed Update the parsing of the lxvp and stxvp instructions that were previously added. lxvp Load VSX Vector Paired stxvp Store VSX Vector Paired A couple of format changes for the arguments to the calculate_prefix_EA function. Add comments to the else if and case statement to clarify which instructions meet this condition. commit 4e75ca1578fab30c02db29fdc3c91b7a66430492 Author: Carl Love <c...@us.ibm.com> Date: Tue Sep 22 12:30:43 2020 -0500 Add ISA 3.1 Set Boolean Extension instruction support Add support for the new ISA 3.1 set boolean condition word instructions: setbc Set Boolean Condition setbcr Set Boolean Condition Reverse setnbc Set Negative Boolean Condition setnbcr Set Negative Boolean Condition Reverse. commit 298a0b02c8a668578bfecd54d298d7c3a3c8127a Author: Carl Love <c...@us.ibm.com> Date: Tue Sep 22 12:25:14 2020 -0500 Add ISA 3.1 Byte-Reverse Instruction support Add support for the new ISA 3.1 word instructions: brd Byte-Reverse Doubleword brh Byte-Reverse Halfword brw Byte-Reverse Word -- You are receiving this mail because: You are watching all bug changes.