On 2022/5/25 10:03, Baolu Lu wrote:
diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
index 4de960834a1b..1c3cf267934d 100644
--- a/drivers/iommu/intel/dmar.c
+++ b/drivers/iommu/intel/dmar.c
@@ -1126,6 +1126,10 @@ static int alloc_iommu(struct dmar_drhd_unit
*drhd)
raw_spin_lock_init(&iommu->register_lock);
+ /* Supports full 20-bit PASID in scalable mode. */
+ if (ecap_pasid(iommu->ecap))
+ iommu->iommu.pasids = 1UL << 20;
+
supported pasid bits is reported by ecap_pss(). I don't think we should
assume 20bits here.
Yes. I overlooked this. Thanks for reminding.
Another thing I need to improve is that scalable mode could be disabled.
This field should be 0 in that case.
I will change above to:
+ /*
+ * A value of N in PSS field of eCap register indicates hardware
+ * supports PASID field of N+1 bits.
+ */
+ if (pasid_supported(iommu))
+ iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap);
Best regards,
baolu
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