> From: Jason Gunthorpe <j...@nvidia.com>
> Sent: Wednesday, April 6, 2022 6:58 AM
>
> On Tue, Apr 05, 2022 at 01:50:36PM -0600, Alex Williamson wrote:
> > >
> > > +static bool intel_iommu_enforce_cache_coherency(struct
> iommu_domain *domain)
> > > +{
> > > + struct dmar_domain *dmar_domain = to_dmar_domain(domain);
> > > +
> > > + if (!dmar_domain->iommu_snooping)
> > > + return false;
> > > + dmar_domain->enforce_no_snoop = true;
> > > + return true;
> > > +}
> >
> > Don't we have issues if we try to set DMA_PTE_SNP on DMARs that don't
> > support it, ie. reserved register bit set in pte faults?
>
> The way the Intel driver is setup that is not possible. Currently it
> does:
>
> static bool intel_iommu_capable(enum iommu_cap cap)
> {
> if (cap == IOMMU_CAP_CACHE_COHERENCY)
> return domain_update_iommu_snooping(NULL);
>
> Which is a global property unrelated to any device.
>
> Thus either all devices and all domains support iommu_snooping, or
> none do.
>
> It is unclear because for some reason the driver recalculates this
> almost constant value on every device attach..
The reason is simply because iommu capability is a global flag 😉
when the cap is removed by this series I don't think we need keep that
global recalculation thing.
Thanks
Kevin
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