On 12/8/21 02:52, Sean Christopherson wrote:
+       /*
+        * Unload the AVIC when the vCPU is about to block,_before_  the vCPU
+        * actually blocks.  The vCPU needs to be marked IsRunning=0 before the
+        * final pass over the vIRR via kvm_vcpu_check_block().  Any IRQs that
+        * arrive before IsRunning=0 will not signal the doorbell, i.e. it's
+        * KVM's responsibility to ensure there are no pending IRQs in the vIRR
+        * after IsRunning is cleared, prior to scheduling out the vCPU.

I prefer to phrase this around paired memory barriers and the usual store/smp_mb/load lockless idiom:

        /*
         * Unload the AVIC when the vCPU is about to block, _before_
         * the vCPU actually blocks.
         *
         * Any IRQs that arrive before IsRunning=0 will not cause an
         * incomplete IPI vmexit on the source, therefore vIRR will also
         * be checked by kvm_vcpu_check_block() before blocking.  The
         * memory barrier implicit in set_current_state orders writing
         * IsRunning=0 before reading the vIRR.  The processor needs a
         * matching memory barrier on interrupt delivery between writing
         * IRR and reading IsRunning; the lack of this barrier might be
         * the cause of errata #1235).
         */

Is there any nuance that I am missing?

Paolo

+        */
+       avic_vcpu_put(vcpu);
+

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