Hi Jason,
On Mon, 10 May 2021 13:39:56 -0300, Jason Gunthorpe <j...@nvidia.com> wrote:
> I still think it is smarter to push a group of RID's into a global
> allocation group and accept there are potential downsides with that
> than to try to force a global allocation group on every RID and then
> try to fix the mess that makes for non-ENQCMD devices.
The proposed ioasid_set change in this set has a token for each set of
IOASIDs.
/**
* struct ioasid_set - Meta data about ioasid_set
* @nh: List of notifiers private to that set
* @xa: XArray to store ioasid_set private IDs, can be used for
* guest-host IOASID mapping, or just a private IOASID namespace.
* @token: Unique to identify an IOASID set
* @type: Token types
* @quota: Max number of IOASIDs can be allocated within the set
* @nr_ioasids: Number of IOASIDs currently allocated in the set
* @id: ID of the set
*/
struct ioasid_set {
struct atomic_notifier_head nh;
struct xarray xa;
void *token;
int type;
int quota;
atomic_t nr_ioasids;
int id;
struct rcu_head rcu;
struct misc_cg *misc_cg; /* For misc cgroup accounting */
};
To satisfy your "give me a PASID for this RID" proposal, can we just use
the RID's struct device as the token? Also add a type field to explicitly
indicate global vs per-set(per-RID). i.e.
ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max,
int type, void *private)
Where flags can be:
enum ioasid_hwid_type {
IOASID_HWID_GLOBAL,
IOASID_HWID_PER_SET,
};
We are really talking about the HW IOASID, just a reminder.
Thanks,
Jacob
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