On 21/09/2020 14:58, John Garry wrote:
Could you try to adapt the hacks I sent before,
please? I know they weren't quite right (I have no hardware to test
on
Could the ARM Rev C FVP be used to at least functionally test? Can't
seem to access myself, even though it's gratis...
), but
the basic idea is to fall back to a spinlock if the cmpxchg() fails. The
queueing in the spinlock implementation should avoid the contention.
So I modified that suggested change to get it functioning, and it looks
like this:
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 7196207be7ea..f907b7c233a2 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -560,6 +560,7 @@ struct arm_smmu_cmdq {
atomic_long_t *valid_map;
atomic_t owner_prod;
atomic_t lock;
+ spinlock_t slock;
};
struct arm_smmu_cmdq_batch {
@@ -1378,7 +1379,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct
arm_smmu_device *smmu,
u64 cmd_sync[CMDQ_ENT_DWORDS];
u32 prod;
unsigned long flags;
- bool owner;
+ bool owner, locked = false;
struct arm_smmu_cmdq *cmdq = &smmu->cmdq;
struct arm_smmu_ll_queue llq = {
.max_n_shift = cmdq->q.llq.max_n_shift,
@@ -1387,26 +1388,42 @@ static int arm_smmu_cmdq_issue_cmdlist(struct
arm_smmu_device *smmu,
/* 1. Allocate some space in the queue */
local_irq_save(flags);
- llq.val = READ_ONCE(cmdq->q.llq.val);
do {
u64 old;
- while (!queue_has_space(&llq, n + sync)) {
+ llq.val = READ_ONCE(cmdq->q.llq.val);
+
+ if (queue_has_space(&llq, n + sync))
+ goto try_cas;
+
+ if (locked) {
+ spin_unlock(&cmdq->slock);
+ locked = 0; // added
+ }
+
+ do {
local_irq_restore(flags);
if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq))
dev_err_ratelimited(smmu->dev, "CMDQ
timeout\n");
local_irq_save(flags);
- }
+ } while (!queue_has_space(&llq, n + sync));
+try_cas:
head.cons = llq.cons;
head.prod = queue_inc_prod_n(&llq, n + sync) |
CMDQ_PROD_OWNED_FLAG;
old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val);
- if (old == llq.val)
+ if (old == llq.val) { // was if (old != llq.val)
+ if (locked) // break;
+ spin_unlock(&cmdq->slock);//
break;//
+ }//
- llq.val = old;
+ if (!locked) {
+ spin_lock(&cmdq->slock);
+ locked = true;
+ }
} while (1);
owner = !(llq.prod & CMDQ_PROD_OWNED_FLAG);
head.prod &= ~CMDQ_PROD_OWNED_FLAG;
@@ -3192,6 +3209,7 @@ static int arm_smmu_cmdq_init(struct
arm_smmu_device *smmu)
atomic_set(&cmdq->owner_prod, 0);
atomic_set(&cmdq->lock, 0);
+ spin_lock_init(&cmdq->slock);
bitmap = (atomic_long_t *)bitmap_zalloc(nents, GFP_KERNEL);
if (!bitmap) {
--
2.26.2
I annotated my mods with comments. Maybe those mods would not be as you
intend.
So I'm not sure that we solve the problem of a new CPU coming along and
trying the cmpxchg immediately, while another CPU has the slock and will
try the cmpxchg also.
Anyway, the results are a bit mixed depending on the CPU count, but
generally positive compared to mainline:
CPUs 2 4 8 16 32 64 96
v5.9-rc1 453K 409K 295K 157K 33.6K 9.5K 5.2K
Will's change 459K 414K 281K 131K 44K 15.5K 8.6K
$subject change 481K 406K 305K 190K 81K 30K 18.7K
(Unit is DMA map+unmap per CPU per second, using test harness. Higher is
better.)
Please let me know of any way to progress.
Thanks,
John
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