Hi Sebastian,
On Wed, Jul 01, 2020 at 12:46:31AM +0200, Sebastian Ott wrote:
> The IVRS ACPI table specifies maximum address sizes for I/O virtual
> addresses that can be handled by the IOMMUs in the system. Parse that
> data from the IVRS header to provide aperture information for DMA
> mappings and users of the iommu API.
>
> Changes for V2:
> - use limits in iommu_setup_dma_ops()
> - rebased to current upstream
>
> Sebastian Ott (3):
> iommu/amd: Parse supported address sizes from IVRS
> iommu/amd: Restrict aperture for domains to conform with IVRS
> iommu/amd: Actually enforce geometry aperture
Thanks for the changes. May I ask what the reason for those changes are?
AFAIK all AMD IOMMU implementations (in hardware) support full 64bit
address spaces, and the IVRS table might actually be wrong, limiting the
address space in the worst case to only 32 bit.
Regards,
Joerg
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