On Sun, May 10, 2020 at 11:34:49AM -0700, Linus Torvalds wrote:
> On Sun, May 10, 2020 at 5:26 AM Joerg Roedel <j...@8bytes.org> wrote:
> >
> > The first race condition was around
> > the non-atomic update of the domain page-table root pointer
> > and the variable containing the page-table depth (called
> > mode). This is fixed now be merging page-table root and mode
> > into one 64-bit field which is read/written atomically.
>
> This seems a bit odd.
>
> The pointer part is always page-aligned, and the "mode" is just three bits.
>
> Why isn't it just encoded as one pointer with the low three bits being the
> mode?
>
> The thing is, the 64-bit atomic reads/writes are very expensive on
> 32-bit x86. If it was just a native pointer, it would be much cheaper
> than an "atomic64_t".
Yeah, when I think about it again, you are right. I think I used
atomic64_t just to be on the safe side with memory odering and all. But
in this case it doesn't really matter when a reader observes the
update, it is only important that the reader does not observe one field
updated while the other is not. And that should already be fullfilled
with 64-bit writes on x86-64, like a native pointer write.
I'll send a patch to Qian to test this, just to be sure I am not missing
anything.
Thanks,
Joerg
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