On 2020/3/27 19:53, Tian, Kevin wrote:
From: Jacob Pan <[email protected]>
Sent: Saturday, March 21, 2020 7:28 AM
Signed-off-by: Jacob Pan <[email protected]>
could you elaborate in which scenario this helper function is required?
I added below commit message:
An Intel iommu domain uses 5-level page table by default. If the
iommu that the domain tries to attach supports less page levels,
the top level page tables should be skipped. Add a helper to do
this so that it could be used in other places.
Best regards,
baolu
---
drivers/iommu/intel-pasid.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 22b30f10b396..191508c7c03e 100644
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -500,6 +500,28 @@ int intel_pasid_setup_first_level(struct intel_iommu
*iommu,
}
/*
+ * Skip top levels of page tables for iommu which has less agaw
+ * than default. Unnecessary for PT mode.
+ */
+static inline int iommu_skip_agaw(struct dmar_domain *domain,
+ struct intel_iommu *iommu,
+ struct dma_pte **pgd)
+{
+ int agaw;
+
+ for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
+ *pgd = phys_to_virt(dma_pte_addr(*pgd));
+ if (!dma_pte_present(*pgd)) {
+ return -EINVAL;
+ }
+ }
+ pr_debug_ratelimited("%s: pgd: %llx, agaw %d d_agaw %d\n",
__func__, (u64)*pgd,
+ iommu->agaw, domain->agaw);
+
+ return agaw;
+}
+
+/*
* Set up the scalable mode pasid entry for second only translation type.
*/
int intel_pasid_setup_second_level(struct intel_iommu *iommu,
--
2.7.4
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