On Fri, Mar 16, 2018 at 12:31:36PM +0800, Lu Baolu wrote: > If caching mode is supported, the hardware will cache > none-present or erroneous translation entries. Hence, > software should explicitly invalidate the PASID cache > after a PASID table entry becomes present. We should > issue such invalidation with the PASID value that we > have changed. PASID 0 is not reserved for this case. > > Cc: Jacob Pan <jacob.jun....@linux.intel.com> > Cc: Kevin Tian <kevin.t...@intel.com> > Cc: Sankaran Rajesh <rajesh.sanka...@intel.com> > Suggested-by: Ashok Raj <ashok....@intel.com> > Signed-off-by: Liu Yi L <yi.l....@intel.com> > Signed-off-by: Lu Baolu <baolu...@linux.intel.com> > --- > drivers/iommu/intel-svm.c | 16 ++++++---------- > 1 file changed, 6 insertions(+), 10 deletions(-)
Applied, thanks. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
