Hi Christoffer, On 02/05/2017 09:53, Christoffer Dall wrote: > On Tue, May 2, 2017 at 9:30 AM, Auger Eric <[email protected]> wrote: >> Hi Will, Robin, Jean-Philippe, >> >> I have been working on the integration between user-space emulated >> SMMU-v3 and VFIO in QEMU. At the moment I fail identifying a proper easy >> way to trap page table updates. This is requested to keep the host >> translation structures consistent to guest translation structures. >> >> On Intel VTD there is a so-called "caching mode" (CM, see VTD spec >> paragraph 6.1) that forces the OS to explicitly invalidate caches >> whenever it updates any remapping structure (updates to not-present or >> present entries). Those invalidation commands are used to trap and >> update host structures. This mode was devised for virtualization. I was >> not able to find such "caching mode" on ARM SMMU. Is there any? >> >> If not, do you have any other suggestion, I mean, besides the >> virtio-based solution. >> >> > Worst case, can you make the guest page tables read-only and catch the > faults and propagate changes to SMMU translations?
The issue I foresee is there are up to 4 level of page tables to trap. This would lead to plenty of regions to "translate" on qemu side. Also, besides the 1st level pointed by TTBR found in stage 1 context descriptor, other page regions would be discovered dynamically as mapping are built. To me this is the last resort solution if confirmed feasible. Thanks Eric > > -Christoffer > _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
