On 05/08/2015 04:21 PM, Konrad Rzeszutek Wilk wrote:
On Fri, May 01, 2015 at 01:32:12PM -0500, wda...@nvidia.com wrote:
From: Will Davis <wda...@nvidia.com>
Hi,
This patch series adds DMA APIs to map and unmap a struct resource to and from
a PCI device's IOVA domain, and implements the AMD, Intel, and nommu versions
of these interfaces.
This solves a long-standing problem with the existing DMA-remapping interfaces,
which require that a struct page be given for the region to be mapped into a
device's IOVA domain. This requirement cannot support peer device BAR ranges,
for which no struct pages exist.
The underlying implementations of map_page and map_sg convert the struct page
into its physical address anyway, so we just need a way to route the physical
address of the BAR region to these implementations. The new interfaces do this
by taking the struct resource describing a device's BAR region, from which the
physical address is derived.
The Intel and nommu versions have been verified on a dual Intel Xeon E5405
workstation. I'm in the process of obtaining hardware to test the AMD version
as well. Please review.
Does it work if you boot with 'iommu=soft swiotlb=force' which will mandate
an strict usage of the DMA API?
PCIe peer2peer is borked on all motherboards I've tried. Only writes are
possible. Reads are not supported. I suppose if you have a platform with
only PCI and an IOMMU this would be very useful. Without both read and
write PCIe peer2peer support, this seems unnecessary.
Mark
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