> -----Original Message-----
> From: Intel-wired-lan <[email protected]> On Behalf
> Of Petr Oros
> Sent: Thursday, March 19, 2026 9:53 PM
> To: [email protected]
> Cc: Vecera, Ivan <[email protected]>; Kitszel, Przemyslaw
> <[email protected]>; Eric Dumazet <[email protected]>;
> Kubalewski, Arkadiusz <[email protected]>; Andrew Lunn
> <[email protected]>; Nguyen, Anthony L
> <[email protected]>; Simon Horman <[email protected]>; intel-
> [email protected]; Jakub Kicinski <[email protected]>; Paolo
> Abeni <[email protected]>; David S. Miller <[email protected]>;
> [email protected]
> Subject: [Intel-wired-lan] [PATCH iwl-net v4] ice: fix missing dpll
> notifications for SW pins
> 
> The SMA/U.FL pin redesign (commit 2dd5d03c77e2 ("ice: redesign dpll
> sma/u.fl pins control")) introduced software-controlled pins that wrap
> backing CGU input/output pins, but never updated the notification and
> data paths to propagate pin events to these SW wrappers.
> 
> There are three problems:
> 
> 1) ice_dpll_notify_changes() sends dpll_pin_change_ntf() only for the
>    direct CGU input pin stored in d->active_input.  When the active
>    input changes, SW pins (SMA/U.FL) that wrap the old or new active
>    input never receive a change notification.  As a result, userspace
>    consumers such as synce4l that monitor SMA pins via dpll netlink
>    never learn when the pin state transitions (e.g. from SELECTABLE to
>    CONNECTED).
> 
> 2) ice_dpll_phase_offset_get() returns p->phase_offset for non-active
>    SW pins, but this field is never updated for SW pins.  The PPS
> phase
>    offset monitor updates the backing CGU input's phase_offset
>    (p->input->phase_offset), not the SW pin's own field.  As a result
>    non-active SW pins always report zero phase offset even when the
>    backing CGU input has valid PPS measurements.
> 
> 3) ice_dpll_pins_notify_mask() does not propagate phase offset change
>    notifications to SW pins either.  When a HW CGU pin gets a phase
>    offset change notification, the SMA/U.FL pin wrapping it is never
>    notified, so userspace consumers (ts2phc, synce4l) monitoring SW
>    pins via dpll netlink never receive phase offset updates.
> 
> Fix all three by:
> 
>  - In ice_dpll_phase_offset_get(), return the backing CGU input's
>    phase_offset for input-direction SW pins instead of the SW pin's
> own
>    (always zero) field.
> 
>  - Introduce ice_dpll_pin_ntf(), a thin wrapper around
>    dpll_pin_change_ntf() that also sends notifications to any
>    registered SMA/U.FL pin whose backing CGU input matches.  Replace
>    all direct dpll_pin_change_ntf() calls in the periodic notification
>    paths with ice_dpll_pin_ntf(), so SW pins are automatically
> notified
>    whenever their backing HW pin is.
> 
> Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
> Signed-off-by: Petr Oros <[email protected]>
> ---
> v4:
>  - expanded scope to also fix phase offset reporting and phase offset
>    notifications for SW pins (problems 2 and 3 above)
>  - replaced ice_dpll_sw_pin_needs_notify() with ice_dpll_pin_ntf(),
>    a unified wrapper that covers all notification paths
>  - squashed into a single patch
> v3: https://lore.kernel.org/all/20260220140700.2910174-1-
> [email protected]/
>  - added kdoc for ice_dpll_sw_pin_needs_notify() helper
> v2: https://lore.kernel.org/all/20260219131500.2271897-1-
> [email protected]/
>  - extracted ice_dpll_sw_pin_needs_notify() helper for readability
>  - moved loop variable into for() scope
> v1: https://lore.kernel.org/all/20260218211414.1411163-1-
> [email protected]/
> ---
>  drivers/net/ethernet/intel/ice/ice_dpll.c | 47 +++++++++++++++++-----
> -
>  1 file changed, 36 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 62f75701d65205..5cfa19da099bfc 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -1915,7 +1915,10 @@ ice_dpll_phase_offset_get(const struct dpll_pin
> *pin, void *pin_priv,
>                                      d->active_input == p->input->pin))
>               *phase_offset = d->phase_offset *
> ICE_DPLL_PHASE_OFFSET_FACTOR;
>       else if (d->phase_offset_monitor_period)

...

> 
>  resched:
> --
> 2.52.0


Reviewed-by: Aleksandr Loktionov <[email protected]>

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