> -----Original Message----- > From: Intel-wired-lan <[email protected]> On Behalf Of Jacob > Keller > Sent: 02 May 2025 04:24 > To: Intel Wired LAN <[email protected]>; Nguyen, Anthony L > <[email protected]>; netdev <[email protected]> > Cc: Keller, Jacob E <[email protected]>; Kubiak, Michal > <[email protected]>; Loktionov, Aleksandr > <[email protected]>; Kolacinski, Karol > <[email protected]>; Kitszel, > Przemyslaw > <[email protected]>; Olech, Milena <[email protected]>; Paul > Menzel <[email protected]> > Subject: [Intel-wired-lan] [PATCH v4 03/15] ice: fix E825-C TSPLL register > definitions > > The E825-C hardware has a slightly different register layout for register 19 of the Clock Generation Unit and TSPLL. The fbdiv_intgr value can be 10 bits wide. > > Additionally, most of the fields that were in register 24 are made available > in register 23 instead. The programming logic already has a corrected > definition for register 23, but it incorrectly still used the 8-bit > definition of fbdiv_intgr. This results in truncating some of the values of > fbdiv_intgr, including the value used for the 156.25MHz signal. > > The driver only used register 24 to obtain the enable status, which we should > read from register 23. This results in an incorrect output for the log > messages, but does not change any functionality besides disabled-by-default > dynamic debug messages. > > Fix the register definitions, and adjust the code to properly reflect the > enable/disable status in the log messages. > > Co-developed-by: Karol Kolacinski <[email protected]> > Signed-off-by: Karol Kolacinski <[email protected]> > Signed-off-by: Jacob Keller <[email protected]> > --- > drivers/net/ethernet/intel/ice/ice_common.h | 17 ++++++++++++++++- > drivers/net/ethernet/intel/ice/ice_tspll.c | 17 +++++++---------- > 2 files changed, 23 insertions(+), 11 deletions(-) >
Tested-by: Rinitha S <[email protected]> (A Contingent worker at Intel)
