Allow to bind two pins and become a single source of clock signal, where
first of the pins is carring the base frequency and second provides SYNC
pulses.
Verify pins bind state/capabilities:
$ ./tools/net/ynl/pyynl/cli.py \
--spec Documentation/netlink/specs/dpll.yaml \
--do pin-get \
--json '{"id":0}'
{'board-label': 'CVL-SDP22',
'id': 0,
[...]
'reference-sync': [{'id': 1, 'state': 'disconnected'}],
[...]}
Bind the pins by setting connected state between them:
$ ./tools/net/ynl/pyynl/cli.py \
--spec Documentation/netlink/specs/dpll.yaml \
--do pin-set \
--json '{"id":0, "reference-sync":{"id":1, "state":"connected"}}'
Verify pins bind state:
$ ./tools/net/ynl/pyynl/cli.py \
--spec Documentation/netlink/specs/dpll.yaml \
--do pin-get \
--json '{"id":0}'
{'board-label': 'CVL-SDP22',
'id': 0,
[...]
'reference-sync': [{'id': 1, 'state': 'connected'}],
[...]}
Unbind the pins by setting disconnected state between them:
$ ./tools/net/ynl/pyynl/cli.py \
--spec Documentation/netlink/specs/dpll.yaml \
--do pin-set \
--json '{"id":0, "reference-sync":{"id":1, "state":"disconnected"}}'
Arkadiusz Kubalewski (3):
dpll: add reference-sync netlink attribute
dpll: add reference sync get/set
ice: add ref-sync dpll pins
Documentation/netlink/specs/dpll.yaml | 19 ++
drivers/dpll/dpll_core.c | 27 +++
drivers/dpll/dpll_core.h | 1 +
drivers/dpll/dpll_netlink.c | 188 ++++++++++++++++--
drivers/dpll/dpll_nl.c | 10 +-
drivers/dpll/dpll_nl.h | 1 +
.../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +
drivers/net/ethernet/intel/ice/ice_dpll.c | 186 +++++++++++++++++
include/linux/dpll.h | 10 +
include/uapi/linux/dpll.h | 1 +
10 files changed, 425 insertions(+), 20 deletions(-)
base-commit: 420aabef3ab5fa743afb4d3d391f03ef0e777ca8
--
2.38.1
